Hi! It's Clarence, the author of (most of) the code in this repository. This repository contains code from EE2026, AY24/25 Semester 2, taken under Dr Chua Dingjuan. I would like to say that I enjoyed this module, particularly in the earlier half of the semester. However, the project is quite hellish... I think I lost most of my interest in working on FPGAs, sadly.
My iteration of the module had us doing 3 assignments, based on the concepts we learnt in the lab sessions. Grade breakdowns of the assignments were:
- A1 (3%)
- A2 (6%)
- A3 (10%)
Generally, assignments were quite simple, and could be done easily after following the lab tutor's instructions.
The code in each assignment folder: A1, A2, and A3 are my submissions. I scored full marks for all three assignments.
The Verilog evaluation (or PE, if you will) was a 11% graded component of the module, where we had 1 hour to code the required behavior given in the questions. It was open book, meaning you could bring in reference material and code from previous assignments.
In general, time is quite short (unless you are a genius xd) and you could probably spend about 30-40 minutes programming and the rest for your bitstream generation / testing / debugging.
I highly suggest takers of the module bring in prepared code for useful modules (such as flexible clock modules, counters, adders, etc.)
The code in the Verilog Evaluation folder was my submission during the test, unedited. I scored full 5/5 marks for this evaluation.
The worst part of this module. It is a 30% graded component and was split into two sections, the easier half and the heliish half.
The easier half requires each of your group members (usually 4 of you) to each complete a basic task and integrate the 4 tasks into 1 program, which needs to be demonstrated to your tutor to get credit. No code submission was required, and I am missing the code to upload for archival.
It took me ~4 hours to complete this section. This is spread across 2 weeks, and is quite simple to achieve. However, some time is required for integration (owing to different coding practices used by each member as well as unfamiliarity with Verilog).
If you are taking this module and ask your friends/seniors about it, likely you will hear similar sentiments.
You have 2 weeks to create a Verilog-based project, of which the theme you are free to decide on. My group chose to create a LUDO emulator, with certain twists. You can read more about it inside the EE2026_final_project folder, in the report pdf.
I spent more than 80 hours on this project and am still quite unsatisfied with the final implementation. My advice is to not aim too high and not spend an absurd amount of time on this project. My lab tutor recommended spending about 20 hours per member. (and I spent 80!)
Please do take note of NUS' Plagiarism Policy when referring to this repository. I have uploaded these files for archival purposes and to help any struggling juniors if needed. Please refer, not copy.
If any part of my project is used in yours, please credit us. Let me know if any of the code was useful to you! I would be glad to hear from you.