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martijnbastiaan
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Mar 10, 2026
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martijnbastiaan
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Nice! My fingers are itching for a registerWb refactor, but that'll have to wait.
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| ( Either | ||
| (Index n) | ||
| (Index n, BitVector wordSize, Bytes wordSize) -- Write (index, mask, data) |
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Could you make this a RamOp-like data structure instead of Either?
clash-protocols-memmap/src/Protocols/MemoryMap/Registers/WishboneStandard/Internal.hs
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| | addrMaxInteger < indexMaxInteger = | ||
| clashCompileError | ||
| [I.__i| Address range (#{addrMaxInteger}) is too small to address all #{indexMaxInteger} words of the register. | ||
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| Consider increasing the address width or reducing the number of words.|] |
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Nice! You don't have to change it for this PR, but we should move this check to the memory map verifier. I.e., store how many bits each has on its address bus and then compare it to its stated size. That would give us much better / quicker error messages.
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| -- Address calculation: compute index within addressable range | ||
| relativeAddress = wbM2S.addr - offset | ||
| inRange = relativeAddress <= resize (bitCoerce (maxBound :: Index n)) |
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numConvert? It should bubble up the right constraints, which should also eliminate the clashCompileError AFAIK.
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It was a bit of a conscious decision to use clashCompileError instead of adding the constraints.
I was on the fence about whether I'd prefer having an extra constraint for each memory mapped component and I decided the pollution would be larger than the chance you actually deal with address spaces that are too small.
clash-protocols-memmap/src/Protocols/MemoryMap/Registers/WishboneStandard/Internal.hs
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firmware-support/bittide-hal/src/manual_additions/addressable_buffer.rs
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To have a single way of handling wishbone interfaces for memorymapped peripherals
This causes a bug in vivado that makes synthesis use 50gb of ram and take 56 minutes instead of 15
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What (what did you do)
This PR introduces a component
addressableBytesWbthat supports adding memory mapped memories such asblockRamsWhy (context, issues, etc.)
To be able to more easily integrate blockRam based components in our
clash-protocols-memmapinfrastructure.Dear reviewer (anything you'd like the reviewer to pay close attention to?)
Regarding the rust side I added a HAL that contains a reference of functionality that I would like to have. What was especially problematic was the alignment requirement for
[u8], or any[[u8; N]]that we use to represent bitvectors. Their alignment requirement is 1 byte, where I require the slice to be 4 byte aligned for efficient copying. I tried to offer an interface to create word aligned byte slices withAlignedArraythat would allow the CPU to perform word sized reads and writes, but am not sure if this is the way to go.We faced a related challenge earlier in the
aximodule, but that was trivially fixed withalign_tobecause it has a streaming interface (we always write to the same destination address).AI disclaimer (heads-up for more than inline autocomplete)
The unit test was mostly written with AI.
TODO
Cross-outany that do not applyWrite (regression) testUpdate documentation, includingdocs/Link to existing issue