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Test addressableBytesWb HAL
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Lines changed: 604 additions & 38 deletions

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‎bittide-instances/bittide-instances.cabal‎

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@@ -222,6 +222,7 @@ library
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Bittide.Instances.Pnr.Si539xSpi
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Bittide.Instances.Pnr.Switch
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Bittide.Instances.Pnr.Synchronizer
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Bittide.Instances.Tests.AddressableBytesWb
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Bittide.Instances.Tests.ElasticBufferWb
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Bittide.Instances.Tests.NestedInterconnect
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Bittide.Instances.Tests.RegisterWb
@@ -314,6 +315,7 @@ test-suite unittests
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Tests.Bittide.Instances.Hitl.Utils.OpenOcd
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Tests.Bittide.Instances.Hitl.Utils.Picocom
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Tests.ClockControlWb
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Wishbone.AddressableBytesWb
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Wishbone.Axi
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Wishbone.CaptureUgn
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Wishbone.DnaPortE2

‎bittide-instances/src/Bittide/Instances/MemoryMaps.hs‎

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@@ -25,6 +25,7 @@ import qualified Bittide.Instances.Hitl.Si539xConfiguration as Si539xConfigurati
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import qualified Bittide.Instances.Hitl.SoftUgnDemo.MemoryMaps as SoftUgnDemo
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import qualified Bittide.Instances.Hitl.SwitchDemo.MemoryMaps as SwitchDemo
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import qualified Bittide.Instances.Hitl.SwitchDemoGppe.MemoryMaps as SwitchDemoGppe
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import qualified Bittide.Instances.Tests.AddressableBytesWb as AddressableBytesWb
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import qualified Bittide.Instances.Tests.ElasticBufferWb as ElasticBufferWb
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import qualified Bittide.Instances.Tests.NestedInterconnect as NestedInterconnect
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import qualified Bittide.Instances.Tests.RegisterWb as RegisterWb
@@ -42,7 +43,8 @@ $( do
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-- Add new memory maps here --
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-------------------------------
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let memoryMaps =
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[ ("Ethernet", vexRiscvEthernetMM)
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[ ("AddressableBytesWb", AddressableBytesWb.memoryMap)
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, ("Ethernet", vexRiscvEthernetMM)
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, ("ElasticBufferWbTest", ElasticBufferWb.dutMM)
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, ("Freeze", freezeMM)
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, ("NestedInterconnect", NestedInterconnect.nestedInterconnectMm)

‎bittide-instances/src/Bittide/Instances/Tests/AddressableBytesWb.hs‎

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@@ -0,0 +1,121 @@
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-- SPDX-FileCopyrightText: 2025 Google LLC
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--
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-- SPDX-License-Identifier: Apache-2.0
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module Bittide.Instances.Tests.AddressableBytesWb where
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import Clash.Prelude
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-- Local
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import Bittide.Cpus.Riscv32imc (vexRiscv0)
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import Bittide.DoubleBufferedRam (
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ContentType (Vec),
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wbStorage,
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)
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import Bittide.Instances.Domains (Basic50)
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import Bittide.ProcessingElement (
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PeConfig (..),
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processingElement,
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)
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import Bittide.ProcessingElement.Util (
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vecFromElfData,
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vecFromElfInstr,
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)
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import Bittide.SharedTypes (withBittideByteOrder)
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import Bittide.Wishbone (uartBytes, uartInterfaceWb)
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import Project.FilePath (
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CargoBuildType (Release),
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findParentContaining,
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firmwareBinariesDir,
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)
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import Clash.Class.BitPackC (ByteOrder (BigEndian))
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import Data.Char (chr)
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import Data.Maybe (catMaybes)
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import Protocols
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import Protocols.Idle (idleSource)
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import Protocols.MemoryMap (MemoryMap, Mm, getMMAny)
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import System.Environment (lookupEnv)
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import System.FilePath ((</>))
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import System.IO.Unsafe (unsafePerformIO)
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import Test.Tasty.HUnit (HasCallStack)
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import VexRiscv (DumpVcd (DumpVcd, NoDumpVcd))
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sim :: IO ()
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sim = do
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-- Print the UART output to terminal for debugging
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putStrLn "=== UART Output ==="
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putStrLn simResult
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putStrLn "=================="
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simResult :: String
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simResult = chr . fromIntegral <$> catMaybes uartStream
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where
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uartStream = sampleC def{timeoutAfter = 1000000} dut0
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dut0 :: Circuit () (Df Basic50 (BitVector 8))
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dut0 = Circuit $ ((),) . snd . toSignals dut . ((),) . snd
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{- | An instance connecting a VexRiscv to a UART and an addressable buffer device.
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Uses the Rust test binary.
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-}
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dut :: Circuit (ToConstBwd Mm) (Df Basic50 (BitVector 8))
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dut = dutWithBinary "addressable_bytes_wb_test"
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-- | Parameterized DUT that loads a specific firmware binary.
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dutWithBinary ::
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(HasCallStack) =>
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String ->
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Circuit (ToConstBwd Mm) (Df Basic50 (BitVector 8))
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dutWithBinary binaryName =
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withBittideByteOrder
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$ withClockResetEnable clockGen (resetGenN d2) enableGen
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$ circuit
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$ \mm -> do
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(uartRx, jtag) <- idleSource
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[uartBus, addressableBus] <- processingElement dumpVcd (peConfig binaryName) -< (mm, jtag)
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(uartTx, _uartStatus) <- uartInterfaceWb d2 d2 uartBytes -< (uartBus, uartRx)
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wbStorage "AddressableBuffer" d8 Nothing -< addressableBus
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idC -< uartTx
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where
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dumpVcd =
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unsafePerformIO $ do
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mVal <- lookupEnv "ADDRESSABLE_BYTES_WB_DUMP_VCD"
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case mVal of
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Just s -> pure (DumpVcd s)
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_ -> pure NoDumpVcd
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peConfig binary = unsafePerformIO $ do
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root <- findParentContaining "cabal.project"
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let elfPath = root </> firmwareBinariesDir "riscv32imc" Release </> binary
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pure
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PeConfig
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{ cpu = vexRiscv0
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, depthI = SNat @IMemWords
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, depthD = SNat @DMemWords
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, initI =
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Just
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$ Vec
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$ unsafePerformIO
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$ vecFromElfInstr BigEndian elfPath
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, initD =
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Just
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$ Vec
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$ unsafePerformIO
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$ vecFromElfData BigEndian elfPath
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, iBusTimeout = d0 -- No timeouts on the instruction bus
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, dBusTimeout = d0 -- No timeouts on the data bus
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, includeIlaWb = False
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}
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{-# OPAQUE dutWithBinary #-}
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memoryMap :: MemoryMap
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memoryMap = getMMAny dut0
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where
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dut0 :: Circuit (ToConstBwd Mm, Df System ()) ()
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dut0 = circuit $ \(mm, _df) -> do
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_uart <- dut -< mm
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idC
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type IMemWords = DivRU (256 * 1024) 4
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type DMemWords = DivRU (256 * 1024) 4

‎bittide-instances/tests/Wishbone/AddressableBytesWb.hs‎

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-- SPDX-FileCopyrightText: 2025 Google LLC
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--
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-- SPDX-License-Identifier: Apache-2.0
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5+
module Wishbone.AddressableBytesWb where
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7+
import Clash.Prelude
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9+
import Data.List (isInfixOf)
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import Test.Tasty (TestTree)
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import Test.Tasty.HUnit (Assertion, assertBool, testCase)
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import Test.Tasty.TH (testGroupGenerator)
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import Bittide.Instances.Tests.AddressableBytesWb (simResult)
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case_sim :: Assertion
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case_sim = assertBool msg ("RESULT: OK" `isInfixOf` simResult)
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where
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msg = "Received the following from the CPU over UART:\n" <> simResult
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21+
tests :: TestTree
22+
tests = $(testGroupGenerator)

‎bittide-instances/tests/unittests.hs‎

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Original file line numberDiff line numberDiff line change
@@ -21,6 +21,7 @@ import qualified Tests.Bittide.Instances.Hitl.Utils.MemoryMap as MemoryMap
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import qualified Tests.Bittide.Instances.Hitl.Utils.OpenOcd as OpenOcd
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import qualified Tests.Bittide.Instances.Hitl.Utils.Picocom as Picocom
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import qualified Tests.ClockControlWb as ClockControlWb
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import qualified Wishbone.AddressableBytesWb as AddressableBytesWb
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import qualified Wishbone.Axi as Axi
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import qualified Wishbone.CaptureUgn as CaptureUgn
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import qualified Wishbone.DnaPortE2 as DnaPortE2
@@ -69,7 +70,8 @@ tests =
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]
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, testGroup
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"Unittests"
72-
[ Axi.tests
73+
[ AddressableBytesWb.tests
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, Axi.tests
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, CaptureUgn.tests
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, ClockControlWb.tests
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, DnaPortE2.tests

‎bittide/src/Bittide/DoubleBufferedRam.hs‎

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Original file line numberDiff line numberDiff line change
@@ -8,7 +8,7 @@ module Bittide.DoubleBufferedRam where
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import Clash.Prelude
99

1010
import Data.Maybe
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import Protocols (Ack (Ack), CSignal, Circuit (Circuit), Df, toSignals)
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import Protocols (Ack (Ack), CSignal, Circuit (Circuit), Df, toSignals, (<|))
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import Protocols.Wishbone
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import Bittide.Extra.Maybe
@@ -18,12 +18,14 @@ import Data.Typeable
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import GHC.Stack (HasCallStack)
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import Protocols.MemoryMap (unMemmap)
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import Protocols.MemoryMap.Registers.WishboneStandard (
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addressableBytesWb,
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deviceWb,
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matchEndianness,
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memoryWb,
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registerConfig,
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)
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import qualified Protocols.ReqResp as ReqResp
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data ContentType n a
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= Vec (Vec n a)
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| Blob (MemBlob n (BitSize a))
@@ -82,26 +84,31 @@ wbStorage ::
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( HasCallStack
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, HiddenClockResetEnable dom
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, KnownNat aw
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, KnownNat depth
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, 1 <= depth
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, ?busByteOrder :: ByteOrder
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) =>
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String ->
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SNat depth ->
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Maybe (ContentType depth (Bytes 4)) ->
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Circuit (BitboneMm dom aw) ()
93-
wbStorage memoryName depth initContent =
94+
wbStorage memoryName SNat initContent =
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let ?regByteOrder = BigEndian
9596
in circuit $ \(mm, wbMaster0) -> do
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wbMaster1 <- matchEndianness -< wbMaster0
9798
[wb0] <- deviceWb memoryName -< (mm, wbMaster1)
98-
memoryWb hasClock hasReset (registerConfig "data") ram depth -< wb0
99+
reqresp <- addressableBytesWb regConfig -< wb0
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(reads, writes0) <- ReqResp.partitionEithers -< reqresp
101+
writes1 <- ReqResp.requests <| ReqResp.dropResponse 0 -< writes0
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_vecUnit <- ram -< (reads, writes1)
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idC -< ()
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where
100-
ram = case initContent of
101-
Nothing ->
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blockRamByteAddressableU
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Just content ->
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blockRamByteAddressable @_ @depth content
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regConfig = registerConfig "data"
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ram = ReqResp.fromBlockRamWithMask
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$ case initContent of
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Nothing ->
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blockRamByteAddressableU
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Just content ->
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blockRamByteAddressable @_ @depth content
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{-# OPAQUE wbStorage #-}
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-- | Storage element with a single wishbone port. Allows for word-aligned addresses.

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