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26 changes: 26 additions & 0 deletions bittide-instances/tests/Wishbone/ScatterGather.hs
Original file line number Diff line number Diff line change
Expand Up @@ -73,5 +73,31 @@ case_scatter_gather_c_test = do
where
msg = "Received the following from the CPU over UART:\n" <> simResultC

-- Aligned ringbuffer test simulation
simAlignedRingbuffer :: IO ()
simAlignedRingbuffer = putStr simResultAlignedRingbuffer

simResultAlignedRingbuffer :: (HasCallStack) => String
simResultAlignedRingbuffer = chr . fromIntegral <$> catMaybes uartStream
where
uartStream = sampleC def{timeoutAfter = 200_000} dutNoMM

dutNoMM :: (HasCallStack) => Circuit () (Df System (BitVector 8))
dutNoMM = circuit $ do
mm <- ignoreMM
uartTx <-
withClockResetEnable clockGen (resetGenN d2) enableGen
$ (dutWithBinary "aligned_ringbuffer_test")
-< mm
idC -< uartTx

case_aligned_ringbuffer_test :: Assertion
case_aligned_ringbuffer_test = do
assertBool
msg
("*** ALL TESTS PASSED ***" `isInfixOf` simResultAlignedRingbuffer)
where
msg = "Received the following from the CPU over UART:\n" <> simResultAlignedRingbuffer

tests :: TestTree
tests = $(testGroupGenerator)
11 changes: 11 additions & 0 deletions firmware-binaries/Cargo.lock

Some generated files are not rendered by default. Learn more about how customized files appear on GitHub.

1 change: 1 addition & 0 deletions firmware-binaries/Cargo.toml
Original file line number Diff line number Diff line change
Expand Up @@ -16,6 +16,7 @@ members = [
"examples/c_hello",
"examples/smoltcp_client",

"sim-tests/aligned_ringbuffer_test",
"sim-tests/axi_stream_self_test",
"sim-tests/registerwb_test",
"sim-tests/capture_ugn_test",
Expand Down
21 changes: 21 additions & 0 deletions firmware-binaries/sim-tests/aligned_ringbuffer_test/Cargo.toml
Original file line number Diff line number Diff line change
@@ -0,0 +1,21 @@
# SPDX-FileCopyrightText: 2025 Google LLC
#
# SPDX-License-Identifier: CC0-1.0

[package]
name = "aligned_ringbuffer_test"
version = "0.1.0"
edition = "2021"
license = "Apache-2.0"
authors = ["Google LLC"]

# See more keys and their definitions at https://doc.rust-lang.org/cargo/reference/manifest.html

[dependencies]
riscv-rt = "0.11.0"
bittide-sys = { path = "../../../firmware-support/bittide-sys" }
bittide-hal = { path = "../../../firmware-support/bittide-hal" }
ufmt = "0.2.0"

[build-dependencies]
memmap-generate = { path = "../../../firmware-support/memmap-generate" }
10 changes: 10 additions & 0 deletions firmware-binaries/sim-tests/aligned_ringbuffer_test/build.rs
Original file line number Diff line number Diff line change
@@ -0,0 +1,10 @@
// SPDX-FileCopyrightText: 2025 Google LLC
//
// SPDX-License-Identifier: Apache-2.0

use memmap_generate::build_utils::standard_memmap_build;

fn main() {
standard_memmap_build("ScatterGatherPe.json", "DataMemory", "InstructionMemory");
println!("cargo:rerun-if-changed=build.rs");
}
18 changes: 18 additions & 0 deletions firmware-binaries/sim-tests/aligned_ringbuffer_test/memory.x
Original file line number Diff line number Diff line change
@@ -0,0 +1,18 @@
/*
SPDX-FileCopyrightText: 2025 Google LLC

SPDX-License-Identifier: CC0-1.0
*/

MEMORY
{
IMEM : ORIGIN = 0x80000000, LENGTH = 64K
DMEM : ORIGIN = 0x20000000, LENGTH = 32K
}

REGION_ALIAS("REGION_TEXT", IMEM);
REGION_ALIAS("REGION_RODATA", DMEM);
REGION_ALIAS("REGION_DATA", DMEM);
REGION_ALIAS("REGION_BSS", DMEM);
REGION_ALIAS("REGION_HEAP", DMEM);
REGION_ALIAS("REGION_STACK", DMEM);
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