Modifications to imporove system overall stability

NSEE · Jul 17, 2023 · 4b6f8de · 4b6f8de
1 parent 7abfae9
commit 4b6f8de
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Showing 22 changed files with 146,333 additions and 76,302 deletions.
diff --git a/...Developments/SpaceWire_Channel/Development/SpaceWire_Channel/SPW_CODEC/spwc_codec_pkg.vhd b/...Developments/SpaceWire_Channel/Development/SpaceWire_Channel/SPW_CODEC/spwc_codec_pkg.vhd
@@ -19,9 +19,9 @@ package spwc_codec_pkg is
 	-- Codec Transmitter Implementation = generic implementation (default)
 	constant c_SPWC_TXIMPL          : spw_implementation_type := impl_generic;
 	-- Codec Receiver FIFO Size, in bits = 11 bits, 2kByte (default)
-	constant c_SPWC_RXFIFOSIZE_BITS : integer range 6 to 14   := 11;
+	constant c_SPWC_RXFIFOSIZE_BITS : integer range 6 to 14   := 12;
 	-- Codec Transmitter FIFO Size, in bits = 11 bits, 2kByte (default)
-	constant c_SPWC_TXFIFOSIZE_BITS : integer range 6 to 14   := 11;
+	constant c_SPWC_TXFIFOSIZE_BITS : integer range 6 to 14   := 10;
 
 	-- SpaceWire Light Codec Interface Signals
 

diff --git a/G3U_HW_V02_2GB/Hardware_Project/Avalon/SpaceWire_Channel/SPW_CODEC/spwc_codec_pkg.vhd b/G3U_HW_V02_2GB/Hardware_Project/Avalon/SpaceWire_Channel/SPW_CODEC/spwc_codec_pkg.vhd
@@ -19,9 +19,9 @@ package spwc_codec_pkg is
 	-- Codec Transmitter Implementation = generic implementation (default)
 	constant c_SPWC_TXIMPL          : spw_implementation_type := impl_generic;
 	-- Codec Receiver FIFO Size, in bits = 11 bits, 2kByte (default)
-	constant c_SPWC_RXFIFOSIZE_BITS : integer range 6 to 14   := 11;
+	constant c_SPWC_RXFIFOSIZE_BITS : integer range 6 to 14   := 12;
 	-- Codec Transmitter FIFO Size, in bits = 11 bits, 2kByte (default)
-	constant c_SPWC_TXFIFOSIZE_BITS : integer range 6 to 14   := 11;
+	constant c_SPWC_TXFIFOSIZE_BITS : integer range 6 to 14   := 10;
 
 	-- SpaceWire Light Codec Interface Signals
 

diff --git a/G3U_HW_V02_2GB/Qsys_Project/MebX_Qsys_Project/synthesis/submodules/spwc_codec_pkg.vhd b/G3U_HW_V02_2GB/Qsys_Project/MebX_Qsys_Project/synthesis/submodules/spwc_codec_pkg.vhd
@@ -19,9 +19,9 @@ package spwc_codec_pkg is
 	-- Codec Transmitter Implementation = generic implementation (default)
 	constant c_SPWC_TXIMPL          : spw_implementation_type := impl_generic;
 	-- Codec Receiver FIFO Size, in bits = 11 bits, 2kByte (default)
-	constant c_SPWC_RXFIFOSIZE_BITS : integer range 6 to 14   := 11;
+	constant c_SPWC_RXFIFOSIZE_BITS : integer range 6 to 14   := 12;
 	-- Codec Transmitter FIFO Size, in bits = 11 bits, 2kByte (default)
-	constant c_SPWC_TXFIFOSIZE_BITS : integer range 6 to 14   := 11;
+	constant c_SPWC_TXFIFOSIZE_BITS : integer range 6 to 14   := 10;
 
 	-- SpaceWire Light Codec Interface Signals
 

diff --git a/G3U_HW_V02_2GB/Qsys_Project/software/Simucam_R0_UART/Makefile b/G3U_HW_V02_2GB/Qsys_Project/software/Simucam_R0_UART/Makefile
@@ -216,8 +216,8 @@ CREATE_LINKER_MAP := 1
 # Common arguments for ALT_CFLAGSs
 APP_CFLAGS_DEFINED_SYMBOLS :=
 APP_CFLAGS_UNDEFINED_SYMBOLS :=
-APP_CFLAGS_OPTIMIZATION := -O2
-APP_CFLAGS_DEBUG_LEVEL :=
+APP_CFLAGS_OPTIMIZATION := -O0
+APP_CFLAGS_DEBUG_LEVEL := -g
 APP_CFLAGS_WARNINGS := -Wall
 APP_CFLAGS_USER_FLAGS :=
 

diff --git a/G3U_HW_V02_2GB/Qsys_Project/software/Simucam_R0_UART/Simucam_R0_UART.elf b/G3U_HW_V02_2GB/Qsys_Project/software/Simucam_R0_UART/Simucam_R0_UART.elf
diff --git a/G3U_HW_V02_2GB/Qsys_Project/software/Simucam_R0_UART/Simucam_R0_UART.objdump b/G3U_HW_V02_2GB/Qsys_Project/software/Simucam_R0_UART/Simucam_R0_UART.objdump
diff --git a/G3U_HW_V02_2GB/Qsys_Project/software/Simucam_R0_UART/simucam_definitions.h b/G3U_HW_V02_2GB/Qsys_Project/software/Simucam_R0_UART/simucam_definitions.h
@@ -23,7 +23,7 @@
 
 /* HW and FW release version */
 #define SIMUCAM_RELEASE                 "L6"
-#define SIMUCAM_HW_VERSION              "0.10"
+#define SIMUCAM_HW_VERSION              "0.10.RC2"
 #define SIMUCAM_FW_VERSION              "0.0"
 
 #define N_OF_NFEE       6	/* ONLY for tests */

diff --git a/G3U_HW_V02_2GB/Qsys_Project/software/Simucam_R0_UART_bsp/Makefile b/G3U_HW_V02_2GB/Qsys_Project/software/Simucam_R0_UART_bsp/Makefile
@@ -127,12 +127,18 @@ BSP_ARFLAGS = -src
 # BSP_ASFLAGS in Makefile. 
 BSP_ASFLAGS = -Wa,-gdwarf2
 
+# C/C++ compiler debug level. '-g' provides the default set of debug symbols 
+# typically required to debug a typical application. Omitting '-g' removes 
+# debug symbols from the ELF. This setting defines the value of 
+# BSP_CFLAGS_DEBUG in Makefile. 
+BSP_CFLAGS_DEBUG = -g
+
 # C/C++ compiler optimization level. "-O0" = no optimization,"-O2" = "normal" 
 # optimization, etc. "-O0" is recommended for code that you want to debug since 
 # compiler optimization can remove variables and produce non-sequential 
 # execution of code while debugging. This setting defines the value of 
 # BSP_CFLAGS_OPTIMIZATION in Makefile. 
-BSP_CFLAGS_OPTIMIZATION = -O2
+BSP_CFLAGS_OPTIMIZATION = -O0
 
 # C/C++ compiler warning level. "-Wall" is commonly used.This setting defines 
 # the value of BSP_CFLAGS_WARNINGS in Makefile. 

diff --git a/G3U_HW_V02_2GB/Qsys_Project/software/Simucam_R0_UART_bsp/settings.bsp b/G3U_HW_V02_2GB/Qsys_Project/software/Simucam_R0_UART_bsp/settings.bsp
@@ -2,8 +2,8 @@
 <sch:Settings xmlns:sch="http://www.altera.com/embeddedsw/bsp/schema">
         <BspType>ucosii</BspType>
         <BspVersion>18.1</BspVersion>
-        <BspGeneratedTimeStamp>Apr 9, 2023 9:15:31 PM</BspGeneratedTimeStamp>
-        <BspGeneratedUnixTimeStamp>1681085731823</BspGeneratedUnixTimeStamp>
+        <BspGeneratedTimeStamp>May 22, 2023 10:30:01 AM</BspGeneratedTimeStamp>
+        <BspGeneratedUnixTimeStamp>1684762201961</BspGeneratedUnixTimeStamp>
         <BspGeneratedLocation>.\</BspGeneratedLocation>
         <BspSettingsFile>settings.bsp</BspSettingsFile>
         <SopcDesignFile>..\..\MebX_Qsys_Project.sopcinfo</SopcDesignFile>
@@ -170,7 +170,7 @@
                 <SettingName>hal.linker.interrupt_stack_size</SettingName>
                 <Identifier>none</Identifier>
                 <Type>DecimalNumber</Type>
-                <Value>2048</Value>
+                <Value>4096</Value>
                 <DefaultValue>1024</DefaultValue>
                 <DestinationFile>none</DestinationFile>
                 <Description>Size of the interrupt stack in bytes.</Description>
@@ -314,7 +314,7 @@
                 <SettingName>hal.make.bsp_cflags_debug</SettingName>
                 <Identifier>BSP_CFLAGS_DEBUG</Identifier>
                 <Type>UnquotedString</Type>
-                <Value>none</Value>
+                <Value>-g</Value>
                 <DefaultValue>-g</DefaultValue>
                 <DestinationFile>makefile_variable</DestinationFile>
                 <Description>C/C++ compiler debug level. '-g' provides the default set of debug symbols typically required to debug a typical application. Omitting '-g' removes debug symbols from the ELF. This setting defines the value of BSP_CFLAGS_DEBUG in Makefile.</Description>
@@ -386,7 +386,7 @@
                 <SettingName>hal.make.bsp_cflags_optimization</SettingName>
                 <Identifier>BSP_CFLAGS_OPTIMIZATION</Identifier>
                 <Type>UnquotedString</Type>
-                <Value>-O2</Value>
+                <Value>-O0</Value>
                 <DefaultValue>-O0</DefaultValue>
                 <DestinationFile>makefile_variable</DestinationFile>
                 <Description>C/C++ compiler optimization level. "-O0" = no optimization,"-O2" = "normal" optimization, etc. "-O0" is recommended for code that you want to debug since compiler optimization can remove variables and produce non-sequential execution of code while debugging. This setting defines the value of BSP_CFLAGS_OPTIMIZATION in Makefile.</Description>

diff --git a/G3U_HW_V02_2GB/Qsys_Project/software/Simucam_R0_UART_bsp/summary.html b/G3U_HW_V02_2GB/Qsys_Project/software/Simucam_R0_UART_bsp/summary.html
@@ -22,10 +22,10 @@ <h3>BSP Description</h3>
 <td width="20%" bgcolor="#77BBFF">BSP Version:</td><td>18.1</td>
 </tr>
 <tr mode="wrap">
-<td width="20%" bgcolor="#77BBFF">BSP Generated On:</td><td>Apr 9, 2023 9:15:31 PM</td>
+<td width="20%" bgcolor="#77BBFF">BSP Generated On:</td><td>May 22, 2023 10:30:01 AM</td>
 </tr>
 <tr mode="wrap">
-<td width="20%" bgcolor="#77BBFF">BSP Generated Timestamp:</td><td>1681085731823</td>
+<td width="20%" bgcolor="#77BBFF">BSP Generated Timestamp:</td><td>1684762201961</td>
 </tr>
 <tr mode="wrap">
 <td width="20%" bgcolor="#77BBFF">BSP Generated Location:</td><td>.\</td>
@@ -957,7 +957,7 @@ <h3>Settings</h3>
 <td width="20%">Default Value:</td><td>1024</td>
 </tr>
 <tr>
-<td width="20%">Value:</td><td>2048</td>
+<td width="20%">Value:</td><td>4096</td>
 </tr>
 <tr>
 <td width="20%">Type:</td><td>DecimalNumber</td>
@@ -1254,7 +1254,7 @@ <h3>Settings</h3>
 <td width="20%">Default Value:</td><td>-g</td>
 </tr>
 <tr>
-<td width="20%">Value:</td><td>none</td>
+<td width="20%">Value:</td><td>-g</td>
 </tr>
 <tr>
 <td width="20%">Type:</td><td>UnquotedString</td>
@@ -1308,7 +1308,7 @@ <h3>Settings</h3>
 <td width="20%">Default Value:</td><td>-O0</td>
 </tr>
 <tr>
-<td width="20%">Value:</td><td>-O2</td>
+<td width="20%">Value:</td><td>-O0</td>
 </tr>
 <tr>
 <td width="20%">Type:</td><td>UnquotedString</td>

diff --git a/G3U_HW_V02_2GB/Quartus_Project/MebX_Qsys_Project_m1_ddr2_memory_p0_summary.csv b/G3U_HW_V02_2GB/Quartus_Project/MebX_Qsys_Project_m1_ddr2_memory_p0_summary.csv
@@ -1,29 +1,29 @@
 Core: MebX_Qsys_Project_m1_ddr2_memory_p0 - Instance: SOPC_INST|m1_ddr2_memory
 Path, Setup Margin, Hold Margin
-"Address Command (Slow 900mV 85C Model)",0.194,0.587
-"Bus Turnaround Time (Slow 900mV 85C Model)",5.444,--
-"Core (Slow 900mV 85C Model)",0.372,-0.029
-"Core Recovery/Removal (Slow 900mV 85C Model)",0.624,0.518
+"Address Command (Slow 900mV 85C Model)",0.189,0.587
+"Bus Turnaround Time (Slow 900mV 85C Model)",5.439,--
+"Core (Slow 900mV 85C Model)",0.42,-0.029
+"Core Recovery/Removal (Slow 900mV 85C Model)",1.035,0.529
 "Read Capture (Slow 900mV 85C Model)",0.15,0.102
-"Read Resync (Slow 900mV 85C Model)",2.691,5.347
-"Write (Slow 900mV 85C Model)",-0.085,-0.085
+"Read Resync (Slow 900mV 85C Model)",2.603,5.227
+"Write (Slow 900mV 85C Model)",-0.086,-0.086
 "Write Leveling tDQSS (Slow 900mV 85C Model)",0.392,0.392
 "Write Leveling tDSS/tDSH (Slow 900mV 85C Model)",0.42,0.42
-"Address Command (Slow 900mV 0C Model)",0.181,0.643
-"Bus Turnaround Time (Slow 900mV 0C Model)",5.47,--
-"Core (Slow 900mV 0C Model)",0.58,0.033
-"Core Recovery/Removal (Slow 900mV 0C Model)",0.777,0.498
+"Address Command (Slow 900mV 0C Model)",0.176,0.643
+"Bus Turnaround Time (Slow 900mV 0C Model)",5.465,--
+"Core (Slow 900mV 0C Model)",0.596,0.032
+"Core Recovery/Removal (Slow 900mV 0C Model)",1.238,0.508
 "Read Capture (Slow 900mV 0C Model)",0.152,0.104
-"Read Resync (Slow 900mV 0C Model)",2.739,5.373
+"Read Resync (Slow 900mV 0C Model)",2.652,5.326
 "Write (Slow 900mV 0C Model)",-0.054,-0.054
 "Write Leveling tDQSS (Slow 900mV 0C Model)",0.392,0.392
 "Write Leveling tDSS/tDSH (Slow 900mV 0C Model)",0.42,0.42
-"Address Command (Fast 900mV 0C Model)",0.136,0.827
-"Bus Turnaround Time (Fast 900mV 0C Model)",5.514,--
-"Core (Fast 900mV 0C Model)",0.632,0.141
-"Core Recovery/Removal (Fast 900mV 0C Model)",2.415,0.268
+"Address Command (Fast 900mV 0C Model)",0.134,0.828
+"Bus Turnaround Time (Fast 900mV 0C Model)",5.513,--
+"Core (Fast 900mV 0C Model)",0.612,0.14
+"Core Recovery/Removal (Fast 900mV 0C Model)",2.667,0.278
 "Read Capture (Fast 900mV 0C Model)",0.182,0.134
-"Read Resync (Fast 900mV 0C Model)",3.244,5.882
-"Write (Fast 900mV 0C Model)",-0.07,-0.07
+"Read Resync (Fast 900mV 0C Model)",3.15,5.725
+"Write (Fast 900mV 0C Model)",-0.072,-0.072
 "Write Leveling tDQSS (Fast 900mV 0C Model)",0.392,0.392
 "Write Leveling tDSS/tDSH (Fast 900mV 0C Model)",0.42,0.42
diff --git a/G3U_HW_V02_2GB/Quartus_Project/MebX_Qsys_Project_m2_ddr2_memory_p0_summary.csv b/G3U_HW_V02_2GB/Quartus_Project/MebX_Qsys_Project_m2_ddr2_memory_p0_summary.csv
@@ -1,29 +1,29 @@
 Core: MebX_Qsys_Project_m2_ddr2_memory_p0 - Instance: SOPC_INST|m2_ddr2_memory
 Path, Setup Margin, Hold Margin
-"Address Command (Slow 900mV 85C Model)",0.177,0.574
-"Bus Turnaround Time (Slow 900mV 85C Model)",5.428,--
-"Core (Slow 900mV 85C Model)",0.184,0.094
-"Core Recovery/Removal (Slow 900mV 85C Model)",0.699,0.474
+"Address Command (Slow 900mV 85C Model)",0.178,0.574
+"Bus Turnaround Time (Slow 900mV 85C Model)",5.429,--
+"Core (Slow 900mV 85C Model)",0.215,0.186
+"Core Recovery/Removal (Slow 900mV 85C Model)",1.054,0.516
 "Read Capture (Slow 900mV 85C Model)",0.149,0.101
-"Read Resync (Slow 900mV 85C Model)",2.735,5.344
-"Write (Slow 900mV 85C Model)",-0.085,-0.085
+"Read Resync (Slow 900mV 85C Model)",2.58,5.278
+"Write (Slow 900mV 85C Model)",-0.087,-0.087
 "Write Leveling tDQSS (Slow 900mV 85C Model)",0.392,0.392
 "Write Leveling tDSS/tDSH (Slow 900mV 85C Model)",0.42,0.42
-"Address Command (Slow 900mV 0C Model)",0.159,0.647
-"Bus Turnaround Time (Slow 900mV 0C Model)",5.465,--
-"Core (Slow 900mV 0C Model)",0.379,0.23
-"Core Recovery/Removal (Slow 900mV 0C Model)",0.847,0.46
+"Address Command (Slow 900mV 0C Model)",0.159,0.646
+"Bus Turnaround Time (Slow 900mV 0C Model)",5.464,--
+"Core (Slow 900mV 0C Model)",0.385,0.259
+"Core Recovery/Removal (Slow 900mV 0C Model)",1.214,0.495
 "Read Capture (Slow 900mV 0C Model)",0.152,0.104
-"Read Resync (Slow 900mV 0C Model)",2.847,5.362
-"Write (Slow 900mV 0C Model)",-0.057,-0.057
+"Read Resync (Slow 900mV 0C Model)",2.696,5.31
+"Write (Slow 900mV 0C Model)",-0.058,-0.058
 "Write Leveling tDQSS (Slow 900mV 0C Model)",0.392,0.392
 "Write Leveling tDSS/tDSH (Slow 900mV 0C Model)",0.42,0.42
-"Address Command (Fast 900mV 0C Model)",0.128,0.831
+"Address Command (Fast 900mV 0C Model)",0.128,0.832
 "Bus Turnaround Time (Fast 900mV 0C Model)",5.519,--
-"Core (Fast 900mV 0C Model)",0.662,0.107
-"Core Recovery/Removal (Fast 900mV 0C Model)",2.138,0.262
+"Core (Fast 900mV 0C Model)",0.627,0.139
+"Core Recovery/Removal (Fast 900mV 0C Model)",2.391,0.265
 "Read Capture (Fast 900mV 0C Model)",0.182,0.134
-"Read Resync (Fast 900mV 0C Model)",3.269,5.832
+"Read Resync (Fast 900mV 0C Model)",3.14,5.807
 "Write (Fast 900mV 0C Model)",-0.075,-0.075
 "Write Leveling tDQSS (Fast 900mV 0C Model)",0.392,0.392
 "Write Leveling tDSS/tDSH (Fast 900mV 0C Model)",0.42,0.42
diff --git a/G3U_HW_V02_2GB/Quartus_Project/MebX_Quartus_Project_DE4_530.qws b/G3U_HW_V02_2GB/Quartus_Project/MebX_Quartus_Project_DE4_530.qws
diff --git a/G3U_HW_V02_2GB/Quartus_Project/output_files/MebX_Quartus_Project_DE4_530.done b/G3U_HW_V02_2GB/Quartus_Project/output_files/MebX_Quartus_Project_DE4_530.done
@@ -1 +1 @@
-Sun Apr 09 16:15:03 2023
+Mon May 22 03:20:47 2023
diff --git a/G3U_HW_V02_2GB/Quartus_Project/output_files/MebX_Quartus_Project_DE4_530.fit.summary b/G3U_HW_V02_2GB/Quartus_Project/output_files/MebX_Quartus_Project_DE4_530.fit.summary
@@ -1,18 +1,18 @@
-Fitter Status : Successful - Sun Apr 09 16:03:14 2023
+Fitter Status : Successful - Mon May 22 03:08:53 2023
 Quartus Prime Version : 18.1.0 Build 625 09/12/2018 SJ Standard Edition
 Revision Name : MebX_Quartus_Project_DE4_530
 Top-level Entity Name : MebX_TopLevel
 Family : Stratix IV
 Device : EP4SGX530KH40C2
 Timing Models : Final
 Logic utilization : 56 %
-    Combinational ALUTs : 164,997 / 424,960 ( 39 % )
+    Combinational ALUTs : 165,076 / 424,960 ( 39 % )
     Memory ALUTs : 9,032 / 212,480 ( 4 % )
-    Dedicated logic registers : 146,963 / 424,960 ( 35 % )
-Total registers : 148303
+    Dedicated logic registers : 147,037 / 424,960 ( 35 % )
+Total registers : 148377
 Total pins : 493 / 888 ( 56 % )
 Total virtual pins : 0
-Total block memory bits : 14,813,480 / 21,233,664 ( 70 % )
+Total block memory bits : 14,868,776 / 21,233,664 ( 70 % )
 DSP block 18-bit elements : 8 / 1,024 ( < 1 % )
 Total GXB Receiver Channel PCS : 0 / 24 ( 0 % )
 Total GXB Receiver Channel PMA : 0 / 36 ( 0 % )

diff --git a/G3U_HW_V02_2GB/Quartus_Project/output_files/MebX_Quartus_Project_DE4_530.map.summary b/G3U_HW_V02_2GB/Quartus_Project/output_files/MebX_Quartus_Project_DE4_530.map.summary
@@ -1,16 +1,16 @@
-Analysis & Synthesis Status : Successful - Sun Apr 09 13:33:42 2023
+Analysis & Synthesis Status : Successful - Mon May 22 00:31:09 2023
 Quartus Prime Version : 18.1.0 Build 625 09/12/2018 SJ Standard Edition
 Revision Name : MebX_Quartus_Project_DE4_530
 Top-level Entity Name : MebX_TopLevel
 Family : Stratix IV
 Logic utilization : N/A
-    Combinational ALUTs : 161,784
+    Combinational ALUTs : 161,765
     Memory ALUTs : 7,242
-    Dedicated logic registers : 142,295
-Total registers : 143583
+    Dedicated logic registers : 142,294
+Total registers : 143582
 Total pins : 493
 Total virtual pins : 0
-Total block memory bits : 14,919,222
+Total block memory bits : 14,974,518
 DSP block 18-bit elements : 8
 Total GXB Receiver Channel PCS : 0
 Total GXB Receiver Channel PMA : 0

diff --git a/G3U_HW_V02_2GB/Quartus_Project/output_files/MebX_Quartus_Project_DE4_530.pin b/G3U_HW_V02_2GB/Quartus_Project/output_files/MebX_Quartus_Project_DE4_530.pin
@@ -1286,7 +1286,7 @@ LED_DE4[5]                   : M29       : output : 2.5 V             :
 LED_DE4[6]                   : M30       : output : 2.5 V             :         : 1A        : Y              
 RESERVED_INPUT_WITH_WEAK_PULLUP : M31       :        :                   :         : 1A        :                
 RESERVED_INPUT_WITH_WEAK_PULLUP : M32       :        :                   :         : 1C        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : M33       :        :                   :         : 1C        :                
+FSM_A[0]                     : M33       : output : 2.5 V             :         : 1C        : N              
 RESERVED_INPUT_WITH_WEAK_PULLUP : M34       :        :                   :         : 1C        :                
 VCCA_L                       : M35       : power  :                   : 2.5V    :           :                
 GXB_NC                       : M36       :        :                   :         : QL2       :                
@@ -1327,7 +1327,7 @@ RESERVED_INPUT_WITH_WEAK_PULLUP : N31       :        :                   :
 VCCIO1C                      : N32       : power  :                   : 2.5V    : 1C        :                
 RESERVED_INPUT_WITH_WEAK_PULLUP : N33       :        :                   :         : 1C        :                
 RESERVED_INPUT_WITH_WEAK_PULLUP : N34       :        :                   :         : 1C        :                
-FSM_A[0]                     : N35       : output : 2.5 V             :         : 1C        : N              
+RESERVED_INPUT_WITH_WEAK_PULLUP : N35       :        :                   :         : 1C        :                
 GND                          : N36       : gnd    :                   :         :           :                
 GND                          : N37       : gnd    :                   :         :           :                
 GXB_GND*                     : N38       :        :                   :         : QL2       :                

diff --git a/G3U_HW_V02_2GB/Quartus_Project/output_files/MebX_Quartus_Project_DE4_530.sof b/G3U_HW_V02_2GB/Quartus_Project/output_files/MebX_Quartus_Project_DE4_530.sof