Modifications on the RMAP Echoing for robustness

NSEE · May 22, 2023 · 7abfae9 · 7abfae9
1 parent 13a9d64
commit 7abfae9
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Showing 104 changed files with 84,106 additions and 79,849 deletions.
diff --git a/...P_Echoing/Development/RMAP_Echoing/RMAP_ECHO_CONTROLLER/rmpe_rmap_echo_controller_ent.vhd b/...P_Echoing/Development/RMAP_Echoing/RMAP_ECHO_CONTROLLER/rmpe_rmap_echo_controller_ent.vhd
diff --git a/...Echoing/Development/RMAP_Echoing/RMAP_ECHO_TRANSMITTER/rmpe_rmap_echo_transmitter_ent.vhd b/...Echoing/Development/RMAP_Echoing/RMAP_ECHO_TRANSMITTER/rmpe_rmap_echo_transmitter_ent.vhd
diff --git a/FPGA_Developments/RMAP_Echoing/Development/RMAP_Echoing/rmpe_rmap_echoing_pkg.vhd b/FPGA_Developments/RMAP_Echoing/Development/RMAP_Echoing/rmpe_rmap_echoing_pkg.vhd
@@ -4,41 +4,41 @@ use ieee.numeric_std.all;
 
 package rmpe_rmap_echoing_pkg is
 
-	constant c_RMAP_FIFO_OVERFLOW_EN : std_logic := '0';
-	
-	constant c_RMAP_PACKAGE_ID_INCOMING : std_logic_vector(3 downto 0) := x"0";
-	constant c_RMAP_PACKAGE_ID_OUTGOING : std_logic_vector(3 downto 0) := x"1";
-
-	type t_rmpe_rmap_echoing_spw_fifo_control is record
-		wrdata_flag : std_logic;
-		wrdata_data : std_logic_vector(7 downto 0);
-		wrreq       : std_logic;
-	end record t_rmpe_rmap_echoing_spw_fifo_control;
-
-	type t_rmpe_rmap_echoing_spw_fifo_status is record
-		full : std_logic;
-	end record t_rmpe_rmap_echoing_spw_fifo_status;
-
-	type t_rmpe_rmap_echoing_rmap_fifo_control is record
-		rdreq : std_logic;
-	end record t_rmpe_rmap_echoing_rmap_fifo_control;
-
-	type t_rmpe_rmap_echoing_rmap_fifo_status is record
-		empty       : std_logic;
-		rddata_flag : std_logic;
-		rddata_data : std_logic_vector(7 downto 0);
-	end record t_rmpe_rmap_echoing_rmap_fifo_status;
-
-	type t_rmpe_rmap_echoing_spw_codec_control is record
-		txwrite : std_logic;
-		txflag  : std_logic;
-		txdata  : std_logic_vector(7 downto 0);
-	end record t_rmpe_rmap_echoing_spw_codec_control;
-
-	type t_rmpe_rmap_echoing_spw_codec_status is record
-		txrdy   : std_logic;
-		txhalff : std_logic;
-	end record t_rmpe_rmap_echoing_spw_codec_status;
+    constant c_RMAP_FIFO_OVERFLOW_EN : std_logic := '0';
+
+    constant c_RMAP_PACKAGE_ID_INCOMING : std_logic_vector(3 downto 0) := x"0";
+    constant c_RMAP_PACKAGE_ID_OUTGOING : std_logic_vector(3 downto 0) := x"1";
+
+    type t_rmpe_rmap_echoing_spw_fifo_control is record
+        wrdata_flag : std_logic;
+        wrdata_data : std_logic_vector(7 downto 0);
+        wrreq       : std_logic;
+    end record t_rmpe_rmap_echoing_spw_fifo_control;
+
+    type t_rmpe_rmap_echoing_spw_fifo_status is record
+        full : std_logic;
+    end record t_rmpe_rmap_echoing_spw_fifo_status;
+
+    type t_rmpe_rmap_echoing_rmap_fifo_control is record
+        rdreq : std_logic;
+    end record t_rmpe_rmap_echoing_rmap_fifo_control;
+
+    type t_rmpe_rmap_echoing_rmap_fifo_status is record
+        empty       : std_logic;
+        rddata_flag : std_logic;
+        rddata_data : std_logic_vector(7 downto 0);
+    end record t_rmpe_rmap_echoing_rmap_fifo_status;
+
+    type t_rmpe_rmap_echoing_spw_codec_control is record
+        txwrite : std_logic;
+        txflag  : std_logic;
+        txdata  : std_logic_vector(7 downto 0);
+    end record t_rmpe_rmap_echoing_spw_codec_control;
+
+    type t_rmpe_rmap_echoing_spw_codec_status is record
+        txrdy   : std_logic;
+        txhalff : std_logic;
+    end record t_rmpe_rmap_echoing_spw_codec_status;
 
 end package rmpe_rmap_echoing_pkg;
 

diff --git a/FPGA_Developments/RMAP_Echoing/Development/RMAP_Echoing/rmpe_rmap_echoing_top.vhd b/FPGA_Developments/RMAP_Echoing/Development/RMAP_Echoing/rmpe_rmap_echoing_top.vhd
@@ -17,6 +17,7 @@ use work.rmpe_rmap_echoing_pkg.all;
 entity rmpe_rmap_echoing_top is
     port(
         reset_i                        : in  std_logic                    := '0'; --          --                       reset_sink.reset
+        echo_rst_i                     : in  std_logic                    := '0'; --          --                    echo_rst_sink.reset
         clk_100_i                      : in  std_logic                    := '0'; --          --                clock_sink_100mhz.clk
         rmap_echo_0_echo_en_i          : in  std_logic                    := '0'; --          --       conduit_end_rmap_echo_0_in.echo_en_signal
         rmap_echo_0_echo_id_en_i       : in  std_logic                    := '0'; --          --                                 .echo_id_en_signal
@@ -104,11 +105,14 @@ end entity rmpe_rmap_echoing_top;
 
 architecture rtl of rmpe_rmap_echoing_top is
 
+    -- Signals --
+    signal s_global_rst : std_logic;
+
     -- Alias --
 
     -- Basic Alias
     alias a_avs_clock_i is clk_100_i;
-    alias a_reset_i is reset_i;
+    alias a_reset_i is s_global_rst;
 
     -- Constants --
 
@@ -389,6 +393,12 @@ begin
         port map(
             clk_i                              => a_avs_clock_i,
             rst_i                              => a_reset_i,
+            fee_0_rmap_echo_en_i               => rmap_echo_0_echo_en_i,
+            fee_1_rmap_echo_en_i               => rmap_echo_1_echo_en_i,
+            fee_2_rmap_echo_en_i               => rmap_echo_2_echo_en_i,
+            fee_3_rmap_echo_en_i               => rmap_echo_3_echo_en_i,
+            fee_4_rmap_echo_en_i               => rmap_echo_4_echo_en_i,
+            fee_5_rmap_echo_en_i               => rmap_echo_5_echo_en_i,
             fee_0_rmap_incoming_fifo_status_i  => s_rmap_echo_0_in_fifo_status,
             fee_0_rmap_outgoing_fifo_status_i  => s_rmap_echo_0_out_fifo_status,
             fee_1_rmap_incoming_fifo_status_i  => s_rmap_echo_1_in_fifo_status,
@@ -422,6 +432,9 @@ begin
 
     -- Signals Assignments and Processes --
 
+    -- Global Reset Assignments
+    s_global_rst <= reset_i or echo_rst_i;
+
     -- SpaceWire Channel Codec Configuration
     p_spwc_codec_config : process(a_avs_clock_i, a_reset_i) is
     begin

diff --git a/FPGA_Developments/RMAP_Echoing/Development/RMAP_Echoing_hw.tcl b/FPGA_Developments/RMAP_Echoing/Development/RMAP_Echoing_hw.tcl
@@ -4,7 +4,7 @@
 
 
 # 
-# RMAP_Echoing "RMAP_Echoing" v1.3
+# RMAP_Echoing "RMAP_Echoing" v1.4
 # rfranca 2019.12.21.00:27:05
 # 
 # 
@@ -20,7 +20,7 @@ package require -exact qsys 16.1
 # 
 set_module_property DESCRIPTION ""
 set_module_property NAME RMAP_Echoing
-set_module_property VERSION 1.3
+set_module_property VERSION 1.4
 set_module_property INTERNAL false
 set_module_property OPAQUE_ADDRESS_MAP true
 set_module_property AUTHOR rfranca
@@ -83,6 +83,21 @@ set_interface_property reset_sink SVD_ADDRESS_GROUP ""
 add_interface_port reset_sink reset_i reset Input 1
 
 
+# 
+# connection point echo_rst_sink
+# 
+add_interface echo_rst_sink reset end
+set_interface_property echo_rst_sink associatedClock clock_sink_100mhz
+set_interface_property echo_rst_sink synchronousEdges DEASSERT
+set_interface_property echo_rst_sink ENABLED true
+set_interface_property echo_rst_sink EXPORT_OF ""
+set_interface_property echo_rst_sink PORT_NAME_MAP ""
+set_interface_property echo_rst_sink CMSIS_SVD_VARIABLES ""
+set_interface_property echo_rst_sink SVD_ADDRESS_GROUP ""
+
+add_interface_port echo_rst_sink echo_rst_i reset Input 1
+
+
 # 
 # connection point clock_sink_100mhz
 # 

diff --git a/FPGA_Developments/RMAP_Echoing/Development/Testbench/RMAP_Echoing_tb.cr.mti b/FPGA_Developments/RMAP_Echoing/Development/Testbench/RMAP_Echoing_tb.cr.mti
@@ -25,7 +25,7 @@ Model Technology ModelSim - Intel FPGA Edition vcom 10.5b Compiler 2016.10 Oct
 ** Error (suppressible): D:/rfranca/Development/GitHub/SimuCam_Development/FPGA_Developments/RMAP_Echoing/Development/RMAP_Echoing/RMAP_ECHO_CONTROLLER/rmpe_rmap_echo_controller_ent.vhd(115): (vcom-1272) Length of formal "usedw" is 5; length of actual is 13.
 ** Error: D:/rfranca/Development/GitHub/SimuCam_Development/FPGA_Developments/RMAP_Echoing/Development/RMAP_Echoing/RMAP_ECHO_CONTROLLER/rmpe_rmap_echo_controller_ent.vhd(431): VHDL Compiler exiting
 
-} {14.0 15.0} {}} ../Testbench/rmap_fifo_stimuli.vhd {1 {vcom -work work -2002 -explicit -stats=none D:/rfranca/Development/GitHub/SimuCam_Development4/FPGA_Developments/RMAP_Echoing/Development/Testbench/rmap_fifo_stimuli.vhd
+} {14.0 15.0} {}} ../Testbench/rmap_fifo_stimuli.vhd {1 {vcom -work work -2002 -explicit -stats=none C:/Users/rfranca/Development/GitHub/SimuCam_Development_NFEE/FPGA_Developments/RMAP_Echoing/Development/Testbench/rmap_fifo_stimuli.vhd
 Model Technology ModelSim - Intel FPGA Edition vcom 10.5b Compiler 2016.10 Oct  5 2016
 -- Loading package STANDARD
 -- Loading package TEXTIO
@@ -168,7 +168,7 @@ Model Technology ModelSim - Intel FPGA Edition vcom 10.5b Compiler 2016.10 Oct
 ** Error: D:/rfranca/Development/GitHub/SimuCam_Development/FPGA_Developments/RMAP_Echoing/Development/RMAP_Echoing/RMAP_ECHO_TRANSMITTER/rmpe_rmap_echo_transmitter_ent.vhd(495): Attribute "high" returns type (error); expecting type t_fifo_queue_index.
 ** Error: D:/rfranca/Development/GitHub/SimuCam_Development/FPGA_Developments/RMAP_Echoing/Development/RMAP_Echoing/RMAP_ECHO_TRANSMITTER/rmpe_rmap_echo_transmitter_ent.vhd(712): VHDL Compiler exiting
 
-} {10.0 134.0} {}} ../RMAP_Echoing/RMAP_ECHO_CONTROLLER/altera_ip/scfifo/spacewire_data_sc_fifo/spacewire_data_sc_fifo.vhd {1 {vcom -work work -2002 -explicit -stats=none D:/rfranca/Development/GitHub/SimuCam_Development4/FPGA_Developments/RMAP_Echoing/Development/RMAP_Echoing/RMAP_ECHO_CONTROLLER/altera_ip/scfifo/spacewire_data_sc_fifo/spacewire_data_sc_fifo.vhd
+} {10.0 134.0} {}} ../RMAP_Echoing/RMAP_ECHO_CONTROLLER/altera_ip/scfifo/spacewire_data_sc_fifo/spacewire_data_sc_fifo.vhd {1 {vcom -work work -2002 -explicit -stats=none C:/Users/rfranca/Development/GitHub/SimuCam_Development_NFEE/FPGA_Developments/RMAP_Echoing/Development/RMAP_Echoing/RMAP_ECHO_CONTROLLER/altera_ip/scfifo/spacewire_data_sc_fifo/spacewire_data_sc_fifo.vhd
 Model Technology ModelSim - Intel FPGA Edition vcom 10.5b Compiler 2016.10 Oct  5 2016
 -- Loading package STANDARD
 -- Loading package TEXTIO
@@ -184,7 +184,7 @@ Model Technology ModelSim - Intel FPGA Edition vcom 10.5b Compiler 2016.10 Oct
 -- Compiling entity spacewire_data_sc_fifo
 -- Compiling architecture SYN of spacewire_data_sc_fifo
 
-} {} {}} ../RMAP_Echoing/RMAP_ECHO_CONTROLLER/rmpe_rmap_echo_controller_ent.vhd {1 {vcom -work work -2002 -explicit -stats=none D:/rfranca/Development/GitHub/SimuCam_Development4/FPGA_Developments/RMAP_Echoing/Development/RMAP_Echoing/RMAP_ECHO_CONTROLLER/rmpe_rmap_echo_controller_ent.vhd
+} {} {}} ../RMAP_Echoing/RMAP_ECHO_CONTROLLER/rmpe_rmap_echo_controller_ent.vhd {1 {vcom -work work -2002 -explicit -stats=none C:/Users/rfranca/Development/GitHub/SimuCam_Development_NFEE/FPGA_Developments/RMAP_Echoing/Development/RMAP_Echoing/RMAP_ECHO_CONTROLLER/rmpe_rmap_echo_controller_ent.vhd
 Model Technology ModelSim - Intel FPGA Edition vcom 10.5b Compiler 2016.10 Oct  5 2016
 -- Loading package STANDARD
 -- Loading package TEXTIO
@@ -196,7 +196,7 @@ Model Technology ModelSim - Intel FPGA Edition vcom 10.5b Compiler 2016.10 Oct
 -- Loading entity spacewire_data_sc_fifo
 -- Loading entity rmap_data_sc_fifo
 
-} {} {}} ../RMAP_Echoing/RMAP_ECHO_CONTROLLER/altera_ip/scfifo/rmap_data_sc_fifo/rmap_data_sc_fifo.vhd {1 {vcom -work work -2002 -explicit -stats=none D:/rfranca/Development/GitHub/SimuCam_Development4/FPGA_Developments/RMAP_Echoing/Development/RMAP_Echoing/RMAP_ECHO_CONTROLLER/altera_ip/scfifo/rmap_data_sc_fifo/rmap_data_sc_fifo.vhd
+} {} {}} ../RMAP_Echoing/RMAP_ECHO_CONTROLLER/altera_ip/scfifo/rmap_data_sc_fifo/rmap_data_sc_fifo.vhd {1 {vcom -work work -2002 -explicit -stats=none C:/Users/rfranca/Development/GitHub/SimuCam_Development_NFEE/FPGA_Developments/RMAP_Echoing/Development/RMAP_Echoing/RMAP_ECHO_CONTROLLER/altera_ip/scfifo/rmap_data_sc_fifo/rmap_data_sc_fifo.vhd
 Model Technology ModelSim - Intel FPGA Edition vcom 10.5b Compiler 2016.10 Oct  5 2016
 -- Loading package STANDARD
 -- Loading package TEXTIO
@@ -212,7 +212,7 @@ Model Technology ModelSim - Intel FPGA Edition vcom 10.5b Compiler 2016.10 Oct
 -- Compiling entity rmap_data_sc_fifo
 -- Compiling architecture SYN of rmap_data_sc_fifo
 
-} {} {}} ../RMAP_Echoing/RMAP_ECHO_TRANSMITTER/rmpe_rmap_echo_transmitter_ent.vhd {1 {vcom -work work -2002 -explicit -stats=none D:/rfranca/Development/GitHub/SimuCam_Development4/FPGA_Developments/RMAP_Echoing/Development/RMAP_Echoing/RMAP_ECHO_TRANSMITTER/rmpe_rmap_echo_transmitter_ent.vhd
+} {} {}} ../RMAP_Echoing/RMAP_ECHO_TRANSMITTER/rmpe_rmap_echo_transmitter_ent.vhd {1 {vcom -work work -2002 -explicit -stats=none C:/Users/rfranca/Development/GitHub/SimuCam_Development_NFEE/FPGA_Developments/RMAP_Echoing/Development/RMAP_Echoing/RMAP_ECHO_TRANSMITTER/rmpe_rmap_echo_transmitter_ent.vhd
 Model Technology ModelSim - Intel FPGA Edition vcom 10.5b Compiler 2016.10 Oct  5 2016
 -- Loading package STANDARD
 -- Loading package TEXTIO
@@ -222,7 +222,7 @@ Model Technology ModelSim - Intel FPGA Edition vcom 10.5b Compiler 2016.10 Oct
 -- Compiling entity rmpe_rmap_echo_transmitter_ent
 -- Compiling architecture RTL of rmpe_rmap_echo_transmitter_ent
 
-} {} {}} ../Testbench/testbench_top.vhd {1 {vcom -work work -2002 -explicit -stats=none D:/rfranca/Development/GitHub/SimuCam_Development4/FPGA_Developments/RMAP_Echoing/Development/Testbench/testbench_top.vhd
+} {} {}} ../Testbench/testbench_top.vhd {1 {vcom -work work -2002 -explicit -stats=none C:/Users/rfranca/Development/GitHub/SimuCam_Development_NFEE/FPGA_Developments/RMAP_Echoing/Development/Testbench/testbench_top.vhd
 Model Technology ModelSim - Intel FPGA Edition vcom 10.5b Compiler 2016.10 Oct  5 2016
 -- Loading package STANDARD
 -- Loading package TEXTIO
@@ -234,7 +234,7 @@ Model Technology ModelSim - Intel FPGA Edition vcom 10.5b Compiler 2016.10 Oct
 -- Loading package rmpe_rmap_echoing_pkg
 -- Loading entity rmpe_rmap_echoing_top
 
-} {} {}} ../RMAP_Echoing/rmpe_rmap_echoing_pkg.vhd {1 {vcom -work work -2002 -explicit -stats=none D:/rfranca/Development/GitHub/SimuCam_Development4/FPGA_Developments/RMAP_Echoing/Development/RMAP_Echoing/rmpe_rmap_echoing_pkg.vhd
+} {} {}} ../RMAP_Echoing/rmpe_rmap_echoing_pkg.vhd {1 {vcom -work work -2002 -explicit -stats=none C:/Users/rfranca/Development/GitHub/SimuCam_Development_NFEE/FPGA_Developments/RMAP_Echoing/Development/RMAP_Echoing/rmpe_rmap_echoing_pkg.vhd
 Model Technology ModelSim - Intel FPGA Edition vcom 10.5b Compiler 2016.10 Oct  5 2016
 -- Loading package STANDARD
 -- Loading package TEXTIO
@@ -244,26 +244,26 @@ Model Technology ModelSim - Intel FPGA Edition vcom 10.5b Compiler 2016.10 Oct
 -- Compiling package body rmpe_rmap_echoing_pkg
 -- Loading package rmpe_rmap_echoing_pkg
 
-} {} {}} ../RMAP_Echoing/rmpe_rmap_echoing_top.vhd {1 {vcom -work work -2002 -explicit -stats=none D:/rfranca/Development/GitHub/SimuCam_Development4/FPGA_Developments/RMAP_Echoing/Development/RMAP_Echoing/rmpe_rmap_echoing_top.vhd
+} {} {}} D:/rfranca/Development/GitHub/SimuCam_Development/FPGA_Developments/RMAP_Echoing/Development/RMAP_Echoing/rmpe_rmap_echoing_pkg.vhd {1 {vcom -work work -2002 -explicit -stats=none D:/rfranca/Development/GitHub/SimuCam_Development/FPGA_Developments/RMAP_Echoing/Development/RMAP_Echoing/rmpe_rmap_echoing_pkg.vhd
 Model Technology ModelSim - Intel FPGA Edition vcom 10.5b Compiler 2016.10 Oct  5 2016
 -- Loading package STANDARD
 -- Loading package TEXTIO
 -- Loading package std_logic_1164
 -- Loading package NUMERIC_STD
+-- Compiling package rmpe_rmap_echoing_pkg
+-- Compiling package body rmpe_rmap_echoing_pkg
 -- Loading package rmpe_rmap_echoing_pkg
--- Compiling entity rmpe_rmap_echoing_top
--- Compiling architecture rtl of rmpe_rmap_echoing_top
--- Loading entity rmpe_rmap_echo_controller_ent
--- Loading entity rmpe_rmap_echo_transmitter_ent
 
-} {} {}} D:/rfranca/Development/GitHub/SimuCam_Development/FPGA_Developments/RMAP_Echoing/Development/RMAP_Echoing/rmpe_rmap_echoing_pkg.vhd {1 {vcom -work work -2002 -explicit -stats=none D:/rfranca/Development/GitHub/SimuCam_Development/FPGA_Developments/RMAP_Echoing/Development/RMAP_Echoing/rmpe_rmap_echoing_pkg.vhd
+} {} {}} ../RMAP_Echoing/rmpe_rmap_echoing_top.vhd {1 {vcom -work work -2002 -explicit -stats=none C:/Users/rfranca/Development/GitHub/SimuCam_Development_NFEE/FPGA_Developments/RMAP_Echoing/Development/RMAP_Echoing/rmpe_rmap_echoing_top.vhd
 Model Technology ModelSim - Intel FPGA Edition vcom 10.5b Compiler 2016.10 Oct  5 2016
 -- Loading package STANDARD
 -- Loading package TEXTIO
 -- Loading package std_logic_1164
 -- Loading package NUMERIC_STD
--- Compiling package rmpe_rmap_echoing_pkg
--- Compiling package body rmpe_rmap_echoing_pkg
 -- Loading package rmpe_rmap_echoing_pkg
+-- Compiling entity rmpe_rmap_echoing_top
+-- Compiling architecture rtl of rmpe_rmap_echoing_top
+-- Loading entity rmpe_rmap_echo_controller_ent
+-- Loading entity rmpe_rmap_echo_transmitter_ent
 
 } {} {}}