RISC-V: refine fpu reg context offset #1257
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The index 0 and 1 are general register which should depends on _XLEN_. Signed-off-by: wangfei_chen <[email protected]>
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There are the following 4 possible configurations and the corressponding offsets: The correct formula to calculate the offset should be |
Signed-off-by: Gaurav Aggarwal <[email protected]>
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aggarg
approved these changes
Mar 13, 2025
aggarg
approved these changes
Mar 13, 2025
tony-josi-aws
approved these changes
Mar 13, 2025
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It looks good to me, thanks for refine. |
kstribrnAmzn
approved these changes
Mar 13, 2025
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The index 0 and 1 are stored for general register which should depends on XLEN.
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