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SaiiijchanSaiiijchan
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RISC-V: refine fpu reg context offset (#1257)
RISC-V: refine fpu reg context offset pxCode and mstatus stored at index 0 and 1 are based on XLEN. Therefore, the correct formula to calculate the FPU register index should be ( ( 2 * portWORD_SIZE ) + ( regIndex * portFPU_REG_SIZE ) ). Signed-off-by: wangfei_chen <[email protected]>
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‎portable/GCC/RISC-V/portContext.h

+67-66
Original file line numberDiff line numberDiff line change
@@ -87,6 +87,7 @@
8787

8888
#define portFPU_REG_SIZE ( __riscv_flen / 8 )
8989
#define portFPU_REG_COUNT 33 /* 32 Floating point registers plus one CSR. */
90+
#define portFPU_REG_OFFSET( regIndex ) ( ( 2 * portWORD_SIZE ) + ( regIndex * portFPU_REG_SIZE ) )
9091
#define portFPU_CONTEXT_SIZE ( portFPU_REG_SIZE * portFPU_REG_COUNT )
9192
#else
9293
#error configENABLE_FPU must not be set to 1 if the hardwar does not have FPU
@@ -103,78 +104,78 @@
103104
.macro portcontexSAVE_FPU_CONTEXT
104105
addi sp, sp, -( portFPU_CONTEXT_SIZE )
105106
/* Store the FPU registers. */
106-
store_f f0, 2 * portFPU_REG_SIZE( sp )
107-
store_f f1, 3 * portFPU_REG_SIZE( sp )
108-
store_f f2, 4 * portFPU_REG_SIZE( sp )
109-
store_f f3, 5 * portFPU_REG_SIZE( sp )
110-
store_f f4, 6 * portFPU_REG_SIZE( sp )
111-
store_f f5, 7 * portFPU_REG_SIZE( sp )
112-
store_f f6, 8 * portFPU_REG_SIZE( sp )
113-
store_f f7, 9 * portFPU_REG_SIZE( sp )
114-
store_f f8, 10 * portFPU_REG_SIZE( sp )
115-
store_f f9, 11 * portFPU_REG_SIZE( sp )
116-
store_f f10, 12 * portFPU_REG_SIZE( sp )
117-
store_f f11, 13 * portFPU_REG_SIZE( sp )
118-
store_f f12, 14 * portFPU_REG_SIZE( sp )
119-
store_f f13, 15 * portFPU_REG_SIZE( sp )
120-
store_f f14, 16 * portFPU_REG_SIZE( sp )
121-
store_f f15, 17 * portFPU_REG_SIZE( sp )
122-
store_f f16, 18 * portFPU_REG_SIZE( sp )
123-
store_f f17, 19 * portFPU_REG_SIZE( sp )
124-
store_f f18, 20 * portFPU_REG_SIZE( sp )
125-
store_f f19, 21 * portFPU_REG_SIZE( sp )
126-
store_f f20, 22 * portFPU_REG_SIZE( sp )
127-
store_f f21, 23 * portFPU_REG_SIZE( sp )
128-
store_f f22, 24 * portFPU_REG_SIZE( sp )
129-
store_f f23, 25 * portFPU_REG_SIZE( sp )
130-
store_f f24, 26 * portFPU_REG_SIZE( sp )
131-
store_f f25, 27 * portFPU_REG_SIZE( sp )
132-
store_f f26, 28 * portFPU_REG_SIZE( sp )
133-
store_f f27, 29 * portFPU_REG_SIZE( sp )
134-
store_f f28, 30 * portFPU_REG_SIZE( sp )
135-
store_f f29, 31 * portFPU_REG_SIZE( sp )
136-
store_f f30, 32 * portFPU_REG_SIZE( sp )
137-
store_f f31, 33 * portFPU_REG_SIZE( sp )
107+
store_f f0, portFPU_REG_OFFSET( 0 )( sp )
108+
store_f f1, portFPU_REG_OFFSET( 1 )( sp )
109+
store_f f2, portFPU_REG_OFFSET( 2 )( sp )
110+
store_f f3, portFPU_REG_OFFSET( 3 )( sp )
111+
store_f f4, portFPU_REG_OFFSET( 4 )( sp )
112+
store_f f5, portFPU_REG_OFFSET( 5 )( sp )
113+
store_f f6, portFPU_REG_OFFSET( 6 )( sp )
114+
store_f f7, portFPU_REG_OFFSET( 7 )( sp )
115+
store_f f8, portFPU_REG_OFFSET( 8 )( sp )
116+
store_f f9, portFPU_REG_OFFSET( 9 )( sp )
117+
store_f f10, portFPU_REG_OFFSET( 10 )( sp )
118+
store_f f11, portFPU_REG_OFFSET( 11 )( sp )
119+
store_f f12, portFPU_REG_OFFSET( 12 )( sp )
120+
store_f f13, portFPU_REG_OFFSET( 13 )( sp )
121+
store_f f14, portFPU_REG_OFFSET( 14 )( sp )
122+
store_f f15, portFPU_REG_OFFSET( 15 )( sp )
123+
store_f f16, portFPU_REG_OFFSET( 16 )( sp )
124+
store_f f17, portFPU_REG_OFFSET( 17 )( sp )
125+
store_f f18, portFPU_REG_OFFSET( 18 )( sp )
126+
store_f f19, portFPU_REG_OFFSET( 19 )( sp )
127+
store_f f20, portFPU_REG_OFFSET( 20 )( sp )
128+
store_f f21, portFPU_REG_OFFSET( 21 )( sp )
129+
store_f f22, portFPU_REG_OFFSET( 22 )( sp )
130+
store_f f23, portFPU_REG_OFFSET( 23 )( sp )
131+
store_f f24, portFPU_REG_OFFSET( 24 )( sp )
132+
store_f f25, portFPU_REG_OFFSET( 25 )( sp )
133+
store_f f26, portFPU_REG_OFFSET( 26 )( sp )
134+
store_f f27, portFPU_REG_OFFSET( 27 )( sp )
135+
store_f f28, portFPU_REG_OFFSET( 28 )( sp )
136+
store_f f29, portFPU_REG_OFFSET( 29 )( sp )
137+
store_f f30, portFPU_REG_OFFSET( 30 )( sp )
138+
store_f f31, portFPU_REG_OFFSET( 31 )( sp )
138139
csrr t0, fcsr
139-
store_x t0, 34 * portFPU_REG_SIZE( sp )
140+
store_x t0, portFPU_REG_OFFSET( 32 )( sp )
140141
.endm
141142
/*-----------------------------------------------------------*/
142143

143144
.macro portcontextRESTORE_FPU_CONTEXT
144145
/* Restore the FPU registers. */
145-
load_f f0, 2 * portFPU_REG_SIZE( sp )
146-
load_f f1, 3 * portFPU_REG_SIZE( sp )
147-
load_f f2, 4 * portFPU_REG_SIZE( sp )
148-
load_f f3, 5 * portFPU_REG_SIZE( sp )
149-
load_f f4, 6 * portFPU_REG_SIZE( sp )
150-
load_f f5, 7 * portFPU_REG_SIZE( sp )
151-
load_f f6, 8 * portFPU_REG_SIZE( sp )
152-
load_f f7, 9 * portFPU_REG_SIZE( sp )
153-
load_f f8, 10 * portFPU_REG_SIZE( sp )
154-
load_f f9, 11 * portFPU_REG_SIZE( sp )
155-
load_f f10, 12 * portFPU_REG_SIZE( sp )
156-
load_f f11, 13 * portFPU_REG_SIZE( sp )
157-
load_f f12, 14 * portFPU_REG_SIZE( sp )
158-
load_f f13, 15 * portFPU_REG_SIZE( sp )
159-
load_f f14, 16 * portFPU_REG_SIZE( sp )
160-
load_f f15, 17 * portFPU_REG_SIZE( sp )
161-
load_f f16, 18 * portFPU_REG_SIZE( sp )
162-
load_f f17, 19 * portFPU_REG_SIZE( sp )
163-
load_f f18, 20 * portFPU_REG_SIZE( sp )
164-
load_f f19, 21 * portFPU_REG_SIZE( sp )
165-
load_f f20, 22 * portFPU_REG_SIZE( sp )
166-
load_f f21, 23 * portFPU_REG_SIZE( sp )
167-
load_f f22, 24 * portFPU_REG_SIZE( sp )
168-
load_f f23, 25 * portFPU_REG_SIZE( sp )
169-
load_f f24, 26 * portFPU_REG_SIZE( sp )
170-
load_f f25, 27 * portFPU_REG_SIZE( sp )
171-
load_f f26, 28 * portFPU_REG_SIZE( sp )
172-
load_f f27, 29 * portFPU_REG_SIZE( sp )
173-
load_f f28, 30 * portFPU_REG_SIZE( sp )
174-
load_f f29, 31 * portFPU_REG_SIZE( sp )
175-
load_f f30, 32 * portFPU_REG_SIZE( sp )
176-
load_f f31, 33 * portFPU_REG_SIZE( sp )
177-
load_x t0, 34 * portFPU_REG_SIZE( sp )
146+
load_f f0, portFPU_REG_OFFSET( 0 )( sp )
147+
load_f f1, portFPU_REG_OFFSET( 1 )( sp )
148+
load_f f2, portFPU_REG_OFFSET( 2 )( sp )
149+
load_f f3, portFPU_REG_OFFSET( 3 )( sp )
150+
load_f f4, portFPU_REG_OFFSET( 4 )( sp )
151+
load_f f5, portFPU_REG_OFFSET( 5 )( sp )
152+
load_f f6, portFPU_REG_OFFSET( 6 )( sp )
153+
load_f f7, portFPU_REG_OFFSET( 7 )( sp )
154+
load_f f8, portFPU_REG_OFFSET( 8 )( sp )
155+
load_f f9, portFPU_REG_OFFSET( 9 )( sp )
156+
load_f f10, portFPU_REG_OFFSET( 10 )( sp )
157+
load_f f11, portFPU_REG_OFFSET( 11 )( sp )
158+
load_f f12, portFPU_REG_OFFSET( 12 )( sp )
159+
load_f f13, portFPU_REG_OFFSET( 13 )( sp )
160+
load_f f14, portFPU_REG_OFFSET( 14 )( sp )
161+
load_f f15, portFPU_REG_OFFSET( 15 )( sp )
162+
load_f f16, portFPU_REG_OFFSET( 16 )( sp )
163+
load_f f17, portFPU_REG_OFFSET( 17 )( sp )
164+
load_f f18, portFPU_REG_OFFSET( 18 )( sp )
165+
load_f f19, portFPU_REG_OFFSET( 19 )( sp )
166+
load_f f20, portFPU_REG_OFFSET( 20 )( sp )
167+
load_f f21, portFPU_REG_OFFSET( 21 )( sp )
168+
load_f f22, portFPU_REG_OFFSET( 22 )( sp )
169+
load_f f23, portFPU_REG_OFFSET( 23 )( sp )
170+
load_f f24, portFPU_REG_OFFSET( 24 )( sp )
171+
load_f f25, portFPU_REG_OFFSET( 25 )( sp )
172+
load_f f26, portFPU_REG_OFFSET( 26 )( sp )
173+
load_f f27, portFPU_REG_OFFSET( 27 )( sp )
174+
load_f f28, portFPU_REG_OFFSET( 28 )( sp )
175+
load_f f29, portFPU_REG_OFFSET( 29 )( sp )
176+
load_f f30, portFPU_REG_OFFSET( 30 )( sp )
177+
load_f f31, portFPU_REG_OFFSET( 31 )( sp )
178+
load_x t0, portFPU_REG_OFFSET( 32 )( sp )
178179
csrw fcsr, t0
179180
addi sp, sp, ( portFPU_CONTEXT_SIZE )
180181
.endm

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