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2 changes: 1 addition & 1 deletion configs/config.protectli_vp66xx
Original file line number Diff line number Diff line change
Expand Up @@ -17,7 +17,6 @@ CONFIG_SOFTWARE_CONNECTION_MANAGER=y
CONFIG_IFDTOOL_DISABLE_ME=y
CONFIG_HAVE_ME_BIN=y
CONFIG_ME_REGION_ALLOW_CPU_READ_ACCESS=y
CONFIG_INTEL_ME_DISABLED_HAP=y
CONFIG_DASHARO_PREFER_S3_SLEEP=y
CONFIG_PCIEXP_LANE_ERR_STAT_CLEAR=y
CONFIG_DRIVERS_EFI_VARIABLE_STORE=y
Expand Down Expand Up @@ -57,6 +56,7 @@ CONFIG_EDK2_IPXE_OPTION_NAME="Network Boot and Utilities"
CONFIG_EDK2_SETUP_PASSWORD=y
CONFIG_EDK2_DASHARO_SYSTEM_FEATURES=y
CONFIG_EDK2_DASHARO_SECURITY_OPTIONS=y
CONFIG_EDK2_DASHARO_INTEL_ME_OPTIONS=y
CONFIG_EDK2_DASHARO_USB_CONFIG=y
CONFIG_EDK2_DASHARO_POWER_CONFIG=y
CONFIG_EDK2_FAN_CURVE_OPTION=y
Expand Down
1 change: 1 addition & 0 deletions src/mainboard/protectli/vault_adl_p/Kconfig
Original file line number Diff line number Diff line change
Expand Up @@ -9,6 +9,7 @@ config BOARD_SPECIFIC_OPTIONS
select SUPERIO_ITE_IT8659E
select DRIVERS_UART_8250IO
select DRIVERS_I2C_GENERIC
select DRIVERS_PCIE_GENERIC
select DRIVERS_INTEL_PMC
select FSP_TYPE_IOT # Needed for PchPcieClockGating W/A
select HAVE_ACPI_RESUME
Expand Down
21 changes: 19 additions & 2 deletions src/mainboard/protectli/vault_adl_p/devicetree.cb
Original file line number Diff line number Diff line change
Expand Up @@ -18,7 +18,8 @@ chip soc/intel/alderlake
}"

register "tcc_offset" = "20" # TCC of 80C

register "usb2_wake_enable_bitmap" = "0x0002"
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Should it be in the enable ME commit?

register "usb3_wake_enable_bitmap" = "0x0001"
device domain 0 on
subsystemid 0x8086 0x7270 inherit

Expand Down Expand Up @@ -200,6 +201,10 @@ chip soc/intel/alderlake
.clk_src = 2,
.clk_req = 2,
}"
chip drivers/pcie/generic
register "wake_gpe" = "GPE0_PME_B0"
device pci 00.0 on end
end
end
device ref pcie_rp6 on
register "pch_pcie_rp[PCH_RP(6)]" = "{
Expand All @@ -209,6 +214,10 @@ chip soc/intel/alderlake
.clk_src = 0,
.clk_req = 0,
}"
chip drivers/pcie/generic
register "wake_gpe" = "GPE0_PME_B0"
device pci 00.0 on end
end
end
device ref pcie_rp7 on
register "pch_pcie_rp[PCH_RP(7)]" = "{
Expand All @@ -217,6 +226,10 @@ chip soc/intel/alderlake
.PcieRpL1Substates = L1_SS_DISABLED,
.clk_src = 6,
}"
chip drivers/pcie/generic
register "wake_gpe" = "GPE0_PME_B0"
device pci 00.0 on end
end
end
device ref pcie_rp8 on
register "pch_pcie_rp[PCH_RP(8)]" = "{
Expand All @@ -225,7 +238,11 @@ chip soc/intel/alderlake
.PcieRpL1Substates = L1_SS_DISABLED,
.clk_src = 5,
}"
end
chip drivers/pcie/generic
register "wake_gpe" = "GPE0_PME_B0"
device pci 00.0 on end
end
end
device ref pcie_rp10 on
register "pch_pcie_rp[PCH_RP(10)]" = "{
.flags = PCIE_RP_LTR | PCIE_RP_CLK_REQ_UNUSED,
Expand Down