Add mcxe31b edma support

boards/nxp/frdm_mcxe31b/frdm_mcxe31b-pinctrl.dtsi

@@ -13,6 +13,18 @@
 		};
 	};
 
+	pinmux_lpuart_2: pinmux_lpuart_2 {
+		group1 {
+			pinmux = <PTA9_LPUART2_TX_O>;
+			output-enable;
+		};
+
+		group2 {
+			pinmux = <PTA8_LPUART2_RX>;
+			input-enable;
+		};
+	};
+
 	pinmux_lpuart_5: pinmux_lpuart_5 {
 		group1 {
 			pinmux = <PTE14_LPUART5_TX_O>;

boards/nxp/frdm_mcxe31b/frdm_mcxe31b.dts

@@ -100,6 +100,10 @@
 	clock-frequency = <DT_FREQ_M(160)>;
 };
 
+&edma {
+	status = "okay";
+};
+
 &erm0 {
 	status = "okay";
 };
@@ -120,6 +124,13 @@
 	status = "okay";
 };
 
+&lpuart_2 {
+	pinctrl-0 = <&pinmux_lpuart_2>;
+	pinctrl-names = "default";
+	dmas = <&edma 16 38>, <&edma 17 39>;
+	dma-names = "tx", "rx";
+};
+
 &lpuart_5 {
 	status = "okay";
 	current-speed = <115200>;
@@ -215,3 +226,6 @@
 &adc_0 {
 	status = "okay";
 };
+
+/* Add lpuart2 label to lpuart_2. */
+lpuart2: &lpuart_2 {};

boards/nxp/frdm_mcxe31b/frdm_mcxe31b.yaml

@@ -15,6 +15,7 @@ supported:
   - can
   - gpio
   - rtc
+  - dma
   - watchdog
   - adc
 vendor: nxp

doc/releases/migration-guide-4.4.rst

@@ -275,6 +275,13 @@ Counter
      GPT now uses explicit devicetree properties rather than hardcoded values, allowing
      per-instance customization.
 
+DMA
+===
+
+* Removed the :kconfig:option:`CONFIG_DMA_MCUX_EDMA_V5` (:github:`100341`). This macro previously distinguished between
+  nxp,version(5) and nxp,version(4). It now supports unified maintenance for both versions.
+  Users can modify ``DMA_MCUX_EDMA_V5`` to ``DMA_MCUX_EDMA_V4``.
+
 EEPROM
 ======
 

drivers/dma/CMakeLists.txt

@@ -30,7 +30,6 @@ zephyr_library_sources_ifdef(CONFIG_DMA_MCHP_XEC dma_mchp_xec.c)
 zephyr_library_sources_ifdef(CONFIG_DMA_MCUX_EDMA dma_mcux_edma.c)
 zephyr_library_sources_ifdef(CONFIG_DMA_MCUX_EDMA_V3 dma_mcux_edma.c)
 zephyr_library_sources_ifdef(CONFIG_DMA_MCUX_EDMA_V4 dma_mcux_edma.c)
-zephyr_library_sources_ifdef(CONFIG_DMA_MCUX_EDMA_V5 dma_mcux_edma.c)
 zephyr_library_sources_ifdef(CONFIG_DMA_MCUX_LPC dma_mcux_lpc.c)
 zephyr_library_sources_ifdef(CONFIG_DMA_MCUX_SMARTDMA dma_mcux_smartdma.c)
 zephyr_library_sources_ifdef(CONFIG_DMA_NIOS2_MSGDMA dma_nios2_msgdma.c)

drivers/dma/Kconfig.mcux_edma

@@ -5,42 +5,48 @@
 
 EDMA_COMPAT := $(DT_COMPAT_NXP_MCUX_EDMA)
 REV_PROP := nxp,version
+DMAMUX_PROP:= has-dmamux
 
 config DMA_MCUX_EDMA
 	bool "MCUX DMA driver"
 	default y
 	depends on $(dt_compat_any_has_prop,$(EDMA_COMPAT),$(REV_PROP),2)
 	imply NOCACHE_MEMORY if CPU_HAS_DCACHE
 	help
-	  DMA driver for MCUX series SoCs.
+	  DMA version 2 driver for MCUX series SoCs with EDMA IP.
 
 config DMA_MCUX_EDMA_V3
 	bool "MCUX DMA v3 driver"
 	default y
 	depends on $(dt_compat_any_has_prop,$(EDMA_COMPAT),$(REV_PROP),3)
 	help
-	  DMA version 3 driver for MCUX series SoCs.
+	  DMA version 3 driver for MCUX series SoCs with DMA3 IP.
 
 config DMA_MCUX_EDMA_V4
-	bool "MCUX DMA v4 driver"
+	bool "MCUX DMA UNIFIED driver"
 	default y
-	depends on $(dt_compat_any_has_prop,$(EDMA_COMPAT),$(REV_PROP),4)
+	depends on $(dt_compat_any_has_prop,$(EDMA_COMPAT),$(REV_PROP),4) || \
+	           $(dt_compat_any_has_prop,$(EDMA_COMPAT),$(REV_PROP),5)
 	help
-	  DMA version 4 driver for MCUX series SoCs.
+	  DMA version 4  driver for MCUX Series SoCs Equipped
+	  with Multiple EDMA IPs(EDMA, DMA3, EDMA4, EDMA5).
+	  For the EDMA4 driver, it is compatible with different EDMA IPs
+	  and allows different EDMA IPs to be used within a single project.
+	  However, it required provide additional support in the SDK
+	  device header. Therefore, only new SoCs could use it.
 
-config DMA_MCUX_EDMA_V5
-	bool "MCUX DMA v5 driver"
-	default y
-	depends on $(dt_compat_any_has_prop,$(EDMA_COMPAT),$(REV_PROP),5)
+config DMA_MCUX_EDMA_DMAMUX
+	bool
+	default (DMA_MCUX_EDMA || $(dt_compat_any_has_prop,$(EDMA_COMPAT),$(DMAMUX_PROP),True))
 	help
-	  DMA version 5 driver for MCUX series SoCs.
+	  Automatically enabled when EDMA device tree node has has-dmamux property.
 
 config DMA_MCUX_MAX_DATA_SIZE
 	int
-	default 64 if DMA_MCUX_EDMA_V5 || DMA_MCUX_EDMA_V4 || DMA_MCUX_EDMA_V3
+	default 64 if DMA_MCUX_EDMA_V4 || DMA_MCUX_EDMA_V3
 	default 32
 
-if DMA_MCUX_EDMA || DMA_MCUX_EDMA_V3 || DMA_MCUX_EDMA_V4 || DMA_MCUX_EDMA_V5
+if DMA_MCUX_EDMA || DMA_MCUX_EDMA_V3 || DMA_MCUX_EDMA_V4
 
 config DMA_TCD_QUEUE_SIZE
 	int "number of TCD in a queue for SG mode"
@@ -51,11 +57,12 @@ config DMA_TCD_QUEUE_SIZE
 config DMA_MCUX_TEST_SLOT_START
 	int "test slot start num"
 	depends on (SOC_SERIES_KINETIS_K6X || SOC_SERIES_KINETIS_KE1XF \
-		    || SOC_SERIES_S32K3 || SOC_SERIES_S32ZE || SOC_SERIES_KE1XZ || SOC_SERIES_MCXE24X)
+		    || SOC_SERIES_S32K3 || SOC_SERIES_S32ZE || SOC_SERIES_KE1XZ || SOC_SERIES_MCXE24X \
+		    || SOC_SERIES_MCXE31X)
 	default 58 if SOC_SERIES_KINETIS_K6X
 	default 60 if SOC_SERIES_KINETIS_KE1XF
 	default 60 if SOC_SERIES_KE1XZ
-	default 62 if SOC_SERIES_S32K3 || SOC_SERIES_S32ZE || SOC_SERIES_MCXE24X
+	default 62 if SOC_SERIES_S32K3 || SOC_SERIES_S32ZE || SOC_SERIES_MCXE24X || SOC_SERIES_MCXE31X
 	help
 	  test slot start num
 
@@ -69,4 +76,4 @@ config DMA_MCUX_USE_DTCM_FOR_DMA_DESCRIPTORS
 	  When this option is activated, the descriptors for DMA transfer are
 	  located in the DTCM (Data Tightly Coupled Memory).
 
-endif # DMA_MCUX_EDMA || DMA_MCUX_EDMA_V3 || DMA_MCUX_EDMA_V4 || DMA_MCUX_EDMA_V5
+endif # DMA_MCUX_EDMA || DMA_MCUX_EDMA_V3 || DMA_MCUX_EDMA_V4

drivers/dma/dma_mcux_edma.c

@@ -40,12 +40,6 @@ LOG_MODULE_REGISTER(dma_mcux_edma, CONFIG_DMA_LOG_LEVEL);
 #define HAS_CHANNEL_GAP(n)		DT_INST_NODE_HAS_PROP(n, channel_gap) ||
 #define DMA_MCUX_HAS_CHANNEL_GAP	(DT_INST_FOREACH_STATUS_OKAY(HAS_CHANNEL_GAP) 0)
 
-#if defined(CONFIG_DMA_MCUX_EDMA_V5)
-typedef DMA5_Type DMAx_Type;
-#else
-typedef DMA_Type DMAx_Type;
-#endif
-
 struct dma_mcux_edma_config {
 	DEVICE_MMIO_NAMED_ROM(edma_mmio);
 #if defined(FSL_FEATURE_SOC_DMAMUX_COUNT) && FSL_FEATURE_SOC_DMAMUX_COUNT
@@ -100,7 +94,7 @@ struct dma_mcux_edma_data {
 #define DEV_CFG(dev) \
 	((const struct dma_mcux_edma_config *const)dev->config)
 #define DEV_DATA(dev) ((struct dma_mcux_edma_data *)dev->data)
-#define DEV_BASE(dev) ((DMAx_Type *)DEVICE_MMIO_NAMED_GET(dev, edma_mmio))
+#define DEV_BASE(dev) ((DMA_Type *)DEVICE_MMIO_NAMED_GET(dev, edma_mmio))
 
 #define DEV_CHANNEL_DATA(dev, ch) \
 	((struct call_back *)(&(DEV_DATA(dev)->data_cb[ch])))
@@ -130,24 +124,39 @@ struct dma_mcux_edma_data {
 #else
 #define EDMA_HW_TCD_CH_ACTIVE_MASK    (DMA_CSR_ACTIVE_MASK)
 #endif /* CONFIG_DMA_MCUX_EDMA_V3 */
-#elif defined(CONFIG_DMA_MCUX_EDMA_V4) || defined(CONFIG_DMA_MCUX_EDMA_V5)
+#elif defined(CONFIG_DMA_MCUX_EDMA_V4)
 /* Above macros have been defined in fsl_edma_core.h */
 #define EDMA_HW_TCD_CH_ACTIVE_MASK (DMA_CH_CSR_ACTIVE_MASK)
 #endif
 
 /* Definations for HW TCD fields */
-#if defined(CONFIG_DMA_MCUX_EDMA) || defined(CONFIG_DMA_MCUX_EDMA_V5)
+#if defined(CONFIG_DMA_MCUX_EDMA)
 #define EDMA_HW_TCD_SADDR(dev, ch) (DEV_BASE(dev)->TCD[ch].SADDR)
 #define EDMA_HW_TCD_DADDR(dev, ch) (DEV_BASE(dev)->TCD[ch].DADDR)
 #define EDMA_HW_TCD_BITER(dev, ch) (DEV_BASE(dev)->TCD[ch].BITER_ELINKNO)
 #define EDMA_HW_TCD_CITER(dev, ch) (DEV_BASE(dev)->TCD[ch].CITER_ELINKNO)
 #define EDMA_HW_TCD_CSR(dev, ch)   (DEV_BASE(dev)->TCD[ch].CSR)
-#elif defined(CONFIG_DMA_MCUX_EDMA_V3) || defined(CONFIG_DMA_MCUX_EDMA_V4)
+#elif defined(CONFIG_DMA_MCUX_EDMA_V3)
 #define EDMA_HW_TCD_SADDR(dev, ch) (DEV_BASE(dev)->CH[ch].TCD_SADDR)
 #define EDMA_HW_TCD_DADDR(dev, ch) (DEV_BASE(dev)->CH[ch].TCD_DADDR)
 #define EDMA_HW_TCD_BITER(dev, ch) (DEV_BASE(dev)->CH[ch].TCD_BITER_ELINKNO)
 #define EDMA_HW_TCD_CITER(dev, ch) (DEV_BASE(dev)->CH[ch].TCD_CITER_ELINKNO)
 #define EDMA_HW_TCD_CSR(dev, ch)   (DEV_BASE(dev)->CH[ch].TCD_CSR)
+#elif defined(CONFIG_DMA_MCUX_EDMA_V4)
+/*
+ * For different EDMA IPs, the register read methods vary. Therefore, for devices
+ * incorporating multiple EDMA types, hardware access must be abstracted and unified.
+ */
+#define EDMA_HW_TCD_SADDR(dev, ch) EDMA_TCD_SADDR(EDMA_TCD_BASE((void *)DEV_BASE(dev), ch), \
+						  EDMA_TCD_TYPE((void *)DEV_BASE(dev)))
+#define EDMA_HW_TCD_DADDR(dev, ch) EDMA_TCD_DADDR(EDMA_TCD_BASE((void *)DEV_BASE(dev), ch), \
+				   EDMA_TCD_TYPE((void *)DEV_BASE(dev)))
+#define EDMA_HW_TCD_BITER(dev, ch) EDMA_TCD_BITER(EDMA_TCD_BASE((void *)DEV_BASE(dev), ch), \
+				   EDMA_TCD_TYPE((void *)DEV_BASE(dev)))
+#define EDMA_HW_TCD_CITER(dev, ch) EDMA_TCD_CITER(EDMA_TCD_BASE((void *)DEV_BASE(dev), ch), \
+				   EDMA_TCD_TYPE((void *)DEV_BASE(dev)))
+#define EDMA_HW_TCD_CSR(dev, ch)   EDMA_TCD_CSR(EDMA_TCD_BASE((void *)DEV_BASE(dev), ch), \
+				   EDMA_TCD_TYPE((void *)DEV_BASE(dev)))
 #endif
 
 #if defined(FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET) && FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET
@@ -302,7 +311,6 @@ static void edma_configure_dmamux(const struct device *dev, uint32_t channel,
 	DMAMUX_SetSource(DEV_DMAMUX_BASE(dev, dmamux_idx), dmamux_channel, slot);
 #endif /* nxp_a_on */
 
-	/* dam_imx_rt_set_channel_priority(dev, channel, config); */
 	DMAMUX_EnableChannel(DEV_DMAMUX_BASE(dev, dmamux_idx), dmamux_channel);
 }
 
@@ -358,7 +366,7 @@ static int dma_mcux_edma_configure_sg_loop(const struct device *dev,
 
 	/* Init all TCDs with the para in transfer config and link them. */
 	for (int i = 0; i < CONFIG_DMA_TCD_QUEUE_SIZE; i++) {
-#if defined(CONFIG_DMA_MCUX_EDMA_V5)
+#if defined(CONFIG_DMA_MCUX_EDMA_V4)
 		EDMA_TcdSetTransferConfigExt(DEV_BASE(dev),
 			&DEV_CFG(dev)->tcdpool[channel][i], &data->transferConfig,
 			&DEV_CFG(dev)->tcdpool[channel][(i + 1) %
@@ -464,7 +472,7 @@ static int dma_mcux_edma_configure_basic(const struct device *dev,
 	struct call_back *data = DEV_CHANNEL_DATA(dev, channel);
 	struct dma_mcux_channel_transfer_edma_settings *xfer_settings = &data->transfer_settings;
 	struct dma_block_config *block_config = config->head_block;
-	uint32_t hw_channel;
+	uint32_t hw_channel = dma_mcux_edma_add_channel_gap(dev, channel);
 	int ret = 0;
 
 	/* block_count shall be 1 */
@@ -691,8 +699,7 @@ static int dma_mcux_edma_start(const struct device *dev, uint32_t channel)
 
 	edma_log_dmamux(dev, channel);
 
-#if !defined(CONFIG_DMA_MCUX_EDMA_V3) && !defined(CONFIG_DMA_MCUX_EDMA_V4) \
-	&& !defined(CONFIG_DMA_MCUX_EDMA_V5)
+#if !defined(CONFIG_DMA_MCUX_EDMA_V3) && !defined(CONFIG_DMA_MCUX_EDMA_V4)
 	LOG_DBG("DMA CR 0x%x", DEV_BASE(dev)->CR);
 #endif
 	data->busy = true;
@@ -856,7 +863,7 @@ static int edma_reload_loop(const struct device *dev, uint32_t channel,
 	 */
 	EDMA_ClearChannelStatusFlags(DEV_BASE(dev), channel, kEDMA_DoneFlag);
 	EDMA_HW_TCD_CSR(dev, channel) |= DMA_CSR_ESG_MASK;
-#elif (CONFIG_DMA_MCUX_EDMA_V3 || CONFIG_DMA_MCUX_EDMA_V4 || CONFIG_DMA_MCUX_EDMA_V5)
+#elif (CONFIG_DMA_MCUX_EDMA_V3 || CONFIG_DMA_MCUX_EDMA_V4)
 	/*We have not verified if this issue exist on V3/V4 HW, jut place a holder here. */
 #endif
 	/* TCDs are configured.  Resume DMA */
@@ -951,24 +958,24 @@ static int dma_mcux_edma_get_status(const struct device *dev, uint32_t channel,
 
 	edma_log_dmamux(dev, channel);
 
-#if defined(CONFIG_DMA_MCUX_EDMA_V3) || defined(CONFIG_DMA_MCUX_EDMA_V4)
+#if defined(CONFIG_DMA_MCUX_EDMA_V3)
 	LOG_DBG("DMA MP_CSR 0x%x",  DEV_BASE(dev)->MP_CSR);
 	LOG_DBG("DMA MP_ES 0x%x",   DEV_BASE(dev)->MP_ES);
 	LOG_DBG("DMA CHx_ES 0x%x",  DEV_BASE(dev)->CH[hw_channel].CH_ES);
 	LOG_DBG("DMA CHx_CSR 0x%x", DEV_BASE(dev)->CH[hw_channel].CH_CSR);
 	LOG_DBG("DMA CHx_ES 0x%x",  DEV_BASE(dev)->CH[hw_channel].CH_ES);
 	LOG_DBG("DMA CHx_INT 0x%x", DEV_BASE(dev)->CH[hw_channel].CH_INT);
 	LOG_DBG("DMA TCD_CSR 0x%x", DEV_BASE(dev)->CH[hw_channel].TCD_CSR);
-#elif defined(CONFIG_DMA_MCUX_EDMA_V5)
-	LOG_DBG("DMA MP_CSR 0x%x",  DEV_BASE(dev)->MP_CSR);
-	LOG_DBG("DMA MP_ES 0x%x",   DEV_BASE(dev)->MP_ES);
-	LOG_DBG("DMA CHx_ES 0x%x",  DEV_BASE(dev)->TCD[hw_channel].CH_ES);
-	LOG_DBG("DMA CHx_CSR 0x%x", DEV_BASE(dev)->TCD[hw_channel].CH_CSR);
-	LOG_DBG("DMA CHx_ES 0x%x",  DEV_BASE(dev)->TCD[hw_channel].CH_ES);
-	LOG_DBG("DMA CHx_INT 0x%x", DEV_BASE(dev)->TCD[hw_channel].CH_INT);
-	LOG_DBG("DMA TCD_CSR 0x%x", DEV_BASE(dev)->TCD[hw_channel].CSR);
-	LOG_DBG("DMA TCD_SADDR 0x%x", DEV_BASE(dev)->TCD[hw_channel].SADDR);
-	LOG_DBG("DMA TCD_DADDR 0x%x", DEV_BASE(dev)->TCD[hw_channel].DADDR);
+#elif defined(CONFIG_DMA_MCUX_EDMA_V4)
+	LOG_DBG("DMA MP_CSR 0x%x",  EDMA_MP_BASE(DEV_BASE(dev))->MP_CSR);
+	LOG_DBG("DMA MP_ES 0x%x",   EDMA_MP_BASE(DEV_BASE(dev))->MP_ES);
+	LOG_DBG("DMA CHx_ES 0x%x",  EDMA_CHANNEL_BASE(DEV_BASE(dev), hw_channel)->CH_ES);
+	LOG_DBG("DMA CHx_CSR 0x%x", EDMA_CHANNEL_BASE(DEV_BASE(dev), hw_channel)->CH_CSR);
+	LOG_DBG("DMA CHx_ES 0x%x",  EDMA_CHANNEL_BASE(DEV_BASE(dev), hw_channel)->CH_ES);
+	LOG_DBG("DMA CHx_INT 0x%x", EDMA_CHANNEL_BASE(DEV_BASE(dev), hw_channel)->CH_INT);
+	LOG_DBG("DMA TCD_CSR 0x%x", EDMA_HW_TCD_CSR(dev, hw_channel));
+	LOG_DBG("DMA TCD_SADDR 0x%x", EDMA_HW_TCD_SADDR(dev, hw_channel));
+	LOG_DBG("DMA TCD_DADDR 0x%x", EDMA_HW_TCD_DADDR(dev, hw_channel));
 #else
 	LOG_DBG("DMA CR 0x%x", DEV_BASE(dev)->CR);
 	LOG_DBG("DMA INT 0x%x", DEV_BASE(dev)->INT);
@@ -1126,11 +1133,7 @@ static int dma_mcux_edma_init(const struct device *dev)
 #define CHANNELS_PER_MUX(n)
 #endif
 
-#if defined(CONFIG_DMA_MCUX_EDMA_V5)
-#define DMA_TCD_ALIGN_SIZE	64
-#else
-#define DMA_TCD_ALIGN_SIZE	32
-#endif
+#define DMA_TCD_ALIGN_SIZE	sizeof(edma_tcd_t)
 
 /*
  * Note: the TCD pool *must* be in non cacheable memory. All of the NXP SOCs

dts/arm/nxp/nxp_mcxe31x_common.dtsi

@@ -149,9 +149,13 @@
 	edma: edma@20c000 {
 		#dma-cells = <2>;
 		compatible = "nxp,mcux-edma";
-		reg = <0x20c000 0x19c>;
+		reg = <0x20c000 0x3000>, <0x280000 0x4000>, <0x284000 0x4000>;
+		nxp,version = <4>;
 		dma-channels = <32>;
-		dma-requests = <128>;
+		dma-requests = <64>;
+		has-dmamux;
+		nxp,mem2mem;
+		no-error-irq;
 		interrupts = <4 0>, <5 0>, <6 0>, <7 0>,
 			     <8 0>, <9 0>, <10 0>, <11 0>,
 			     <12 0>, <13 0>, <14 0>, <15 0>,

dts/bindings/dma/nxp,mcux-edma.yaml

@@ -31,6 +31,12 @@ properties:
       DMAMUX. This value is used to validate the request source index provided in the
       DMA specifier.
 
+  has-dmamux:
+    type: boolean
+    description: |
+      Indicates whether the DMA controller has an integrated DMAMUX.
+      If present, the controller includes DMAMUX functionality.
+
   dmamux-reg-offset:
     type: int
     default: 0

modules/hal_nxp/mcux/mcux-sdk-ng/drivers/drivers.cmake

@@ -57,12 +57,11 @@ set_variable_ifdef(CONFIG_COUNTER_MCUX_RTC_JDP  CONFIG_MCUX_COMPONENT_driver.rtc
 set_variable_ifdef(CONFIG_DAC_MCUX_DAC          CONFIG_MCUX_COMPONENT_driver.dac)
 set_variable_ifdef(CONFIG_DAC_MCUX_DAC12        CONFIG_MCUX_COMPONENT_driver.dac12)
 set_variable_ifdef(CONFIG_DAC_MCUX_DAC32        CONFIG_MCUX_COMPONENT_driver.dac32)
-set_variable_ifdef(CONFIG_DMA_MCUX_EDMA         CONFIG_MCUX_COMPONENT_driver.dmamux)
 set_variable_ifdef(CONFIG_DMA_MCUX_EDMA         CONFIG_MCUX_COMPONENT_driver.edma)
 set_variable_ifdef(CONFIG_DMA_MCUX_EDMA_V3      CONFIG_MCUX_COMPONENT_driver.dma3)
 set_variable_ifdef(CONFIG_DMA_MCUX_EDMA_V4      CONFIG_MCUX_COMPONENT_driver.edma4)
+set_variable_ifdef(CONFIG_DMA_MCUX_EDMA_DMAMUX  CONFIG_MCUX_COMPONENT_driver.dmamux)
 set_variable_ifdef(CONFIG_DMA_NXP_EDMA          CONFIG_MCUX_COMPONENT_driver.edma_rev2)
-set_variable_ifdef(CONFIG_DMA_MCUX_EDMA_V5      CONFIG_MCUX_COMPONENT_driver.edma4)
 set_variable_ifdef(CONFIG_EDAC_NXP_EIM          CONFIG_MCUX_COMPONENT_driver.eim)
 set_variable_ifdef(CONFIG_EDAC_NXP_ERM          CONFIG_MCUX_COMPONENT_driver.erm)
 set_variable_ifdef(CONFIG_ENTROPY_MCUX_RNGA     CONFIG_MCUX_COMPONENT_driver.rnga)

tests/drivers/dma/chan_blen_transfer/boards/frdm_mcxe31b.overlay

@@ -0,0 +1,8 @@
+/*
+ * Copyright 2025 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/* Add test label to edma node */
+tst_dma0: &edma {};

tests/drivers/dma/chan_link_transfer/boards/frdm_mcxe31b.overlay

@@ -0,0 +1,8 @@
+/*
+ * Copyright 2025 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/* Add test label to edma node */
+tst_dma0: &edma {};

tests/drivers/dma/chan_link_transfer/testcase.yaml

@@ -8,6 +8,7 @@ tests:
     platform_allow:
       - frdm_k64f
       - frdm_mcxe247
+      - frdm_mcxe31b
       - mimxrt595_evk/mimxrt595s/cm33
       - mimxrt1010_evk
       - mimxrt1050_evk/mimxrt1052/hyperflash

tests/drivers/dma/loop_transfer/boards/frdm_mcxe31b.overlay

@@ -0,0 +1,8 @@
+/*
+ * Copyright 2025 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/* Add test label to edma node */
+tst_dma0: &edma {};