NXP S32 introduce support PSI5 #451
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ping... working to clean things up here. |
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@congnguyenhuu, @manuargue, @Dat-NguyenDuy what are the plans on this PR? |
Hello, there are some suggestions in the Zephyr PR that need to be addressed first. I'm working on it. |
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This is the PSI5 baremetal driver for s32ze Signed-off-by: Cong Nguyen Huu <[email protected]>
Use zephyr .nocache section for non-cacheable variables. Signed-off-by: Cong Nguyen Huu <[email protected]>
Code autogenerated with S32 Design Studio for s32ze Signed-off-by: Cong Nguyen Huu <[email protected]>
Remove 'u' suffix from macros that used with LISTIFY in shim-driver Signed-off-by: Cong Nguyen Huu <[email protected]>
Update the PSI5 clock sources to support bitrates of 125 kbps and 189 kbps, corresponding to 4 MHz and 6 MHz, respectively. Signed-off-by: Cong Nguyen Huu <[email protected]>
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Add baremetal driver for PSI5 on S32ZE devices and headers for PSI5 on SoC S32Z270