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2 files changed +18
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lines changed Original file line number Diff line number Diff line change @@ -201,7 +201,7 @@ typedef struct {
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/** Array initializer of ENET peripheral base addresses */
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#define IP_ENET_BASE_ADDRS { IP_ENET_BASE }
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/** Array initializer of ENET peripheral base pointers */
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- #define IP_ENET_BASE_PTRS { IP_ENET }
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+ #define ENET_BASE_PTRS { IP_ENET }
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/* ----------------------------------------------------------------------------
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-- ENET Register Masks
@@ -1498,6 +1498,16 @@ typedef struct {
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* @}
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*/ /* end of group ENET_Register_Masks */
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+ /* ENET Buffer Descriptor and Buffer Address Alignment. */
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+ #define ENET_BUFF_ALIGNMENT (64U)
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+
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+ /* Interrupt vectors for the ENET peripheral type */
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+ #define ENET_Transmit_IRQS { ENET_TX_Buffer_IRQn }
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+ #define ENET_Receive_IRQS { ENET_RX_Buffer_IRQn }
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+ #define ENET_Error_IRQS { ENET_PRE_IRQn }
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+ #define ENET_1588_Timer_IRQS { ENET_Timer_IRQn }
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+ #define ENET_Ts_IRQS { ENET_Timer_IRQn }
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+
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/*!
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* @}
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*/ /* end of group ENET_Peripheral_Access_Layer */
Original file line number Diff line number Diff line change 29
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#define FSL_FEATURE_SOC_WDOG_COUNT (1)
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/* @brief RTC availability on the SoC. */
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#define FSL_FEATURE_SOC_RTC_COUNT (1)
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+ /* @brief ENET availability on the SoC. */
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+ #define FSL_FEATURE_SOC_ENET_COUNT (1)
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/* SYSMPU module features */
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/* @brief Conversion control count (related to number of registers SC1n and Rn). */
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#define FSL_FEATURE_ADC12_CONVERSION_CONTROL_COUNT (32)
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+ /* ENET module features */
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+
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+ /* @brief Queue Size for each instance. */
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+ #define FSL_FEATURE_ENET_INSTANCE_QUEUEn (x ) (1)
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+
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#endif /* _S32K148_FEATURES_H_ */
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