Skip to content

Commit bf7792b

Browse files
marcin-wierzbickimarcin-wierzbicki
committed
s32: add support for S32K148 SoC
Add support for S32K148 SoC. Drivers enabled: SYSMPU, GPIO, PORT, LPUART, ADC, FlexCAN, FTM, RTC, LMEM, WDOG. Signed-off-by: Marcin Wierzbicki <[email protected]>
1 parent 6d316e7 commit bf7792b

17 files changed

+3342
-495
lines changed

‎s32/drivers/s32k1/BaseNXP/header/S32K148_ADC.h

+22-491
Large diffs are not rendered by default.

‎s32/drivers/s32k1/BaseNXP/header/S32K148_FLEXCAN.h

+4-4
Original file line numberDiff line numberDiff line change
@@ -117,10 +117,10 @@ typedef struct {
117117
__IO uint32_t PL2_PLMASK_HI; /**< Pretended Networking Payload High Filter 2 low order bits / Payload High Mask register, offset: 0xB24 */
118118
uint8_t RESERVED_7[24];
119119
struct { /* offset: 0xB40, array step: 0x10 */
120-
__I uint32_t WMBn_CS; /**< Wake Up Message Buffer register for C/S, array offset: 0xB40, array step: 0x10 */
121-
__I uint32_t WMBn_ID; /**< Wake Up Message Buffer Register for ID, array offset: 0xB44, array step: 0x10 */
122-
__I uint32_t WMBn_D03; /**< Wake Up Message Buffer Register for Data 0-3, array offset: 0xB48, array step: 0x10 */
123-
__I uint32_t WMBn_D47; /**< Wake Up Message Buffer Register Data 4-7, array offset: 0xB4C, array step: 0x10 */
120+
__I uint32_t CS; /**< Wake Up Message Buffer register for C/S, array offset: 0xB40, array step: 0x10 */
121+
__I uint32_t ID; /**< Wake Up Message Buffer Register for ID, array offset: 0xB44, array step: 0x10 */
122+
__I uint32_t D03; /**< Wake Up Message Buffer Register for Data 0-3, array offset: 0xB48, array step: 0x10 */
123+
__I uint32_t D47; /**< Wake Up Message Buffer Register Data 4-7, array offset: 0xB4C, array step: 0x10 */
124124
} WMB[CAN_WMB_COUNT];
125125
uint8_t RESERVED_8[128];
126126
__IO uint32_t FDCTRL; /**< CAN FD Control Register, offset: 0xC00 */

‎s32/mcux/devices/S32K148/S32K148_device.h

+830
Large diffs are not rendered by default.

‎s32/mcux/devices/S32K148/S32K148_features.h

+309
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,309 @@
1+
/*
2+
* Copyright 2023-2024 NXP
3+
*
4+
* SPDX-License-Identifier: BSD-3-Clause
5+
*/
6+
7+
#ifndef _S32K148_FEATURES_H_
8+
#define _S32K148_FEATURES_H_
9+
10+
/* SOC module features */
11+
12+
/* @brief ADC12 availability on the SoC. */
13+
#define FSL_FEATURE_SOC_ADC12_COUNT (2)
14+
/* @brief SYSMPU availability on the SoC. */
15+
#define FSL_FEATURE_SOC_SYSMPU_COUNT (1)
16+
/* @brief PORT availability on the SoC. */
17+
#define FSL_FEATURE_SOC_PORT_COUNT (5)
18+
/* @brief GPIO availability on the SoC. */
19+
#define FSL_FEATURE_SOC_GPIO_COUNT (5)
20+
/* @brief LPUART availability on the SoC. */
21+
#define FSL_FEATURE_SOC_LPUART_COUNT (3)
22+
/* @brief LMEM availability on the SoC. */
23+
#define FSL_FEATURE_SOC_LMEM_COUNT (1)
24+
/* @brief FTM availability on the SoC. */
25+
#define FSL_FEATURE_SOC_FTM_COUNT (8)
26+
/* @brief FLEXCAN availability on the SoC. */
27+
#define FSL_FEATURE_SOC_FLEXCAN_COUNT (3)
28+
/* @brief WDOG availability on the SoC. */
29+
#define FSL_FEATURE_SOC_WDOG_COUNT (1)
30+
/* @brief RTC availability on the SoC. */
31+
#define FSL_FEATURE_SOC_RTC_COUNT (1)
32+
33+
/* SYSMPU module features */
34+
35+
/* @brief Specifies number of descriptors available. */
36+
#define FSL_FEATURE_SYSMPU_DESCRIPTOR_COUNT (16)
37+
/* @brief Has process identifier support. */
38+
#define FSL_FEATURE_SYSMPU_HAS_PROCESS_IDENTIFIER (1)
39+
/* @brief Total number of MPU slave. */
40+
#define FSL_FEATURE_SYSMPU_SLAVE_COUNT (5)
41+
/* @brief Total number of MPU master. */
42+
#define FSL_FEATURE_SYSMPU_MASTER_COUNT (4)
43+
44+
/* PORT module features */
45+
46+
/* @brief Has control lock (register bit PCR[LK]). */
47+
#define FSL_FEATURE_PORT_HAS_PIN_CONTROL_LOCK (1)
48+
/* @brief Has open drain control (register bit PCR[ODE]). */
49+
#define FSL_FEATURE_PORT_HAS_OPEN_DRAIN (0)
50+
/* @brief Has digital filter (registers DFER, DFCR and DFWR). */
51+
#define FSL_FEATURE_PORT_HAS_DIGITAL_FILTER (1)
52+
/* @brief Has DMA request (register bit field PCR[IRQC] values). */
53+
#define FSL_FEATURE_PORT_HAS_DMA_REQUEST (1)
54+
/* @brief Has pull resistor selection available. */
55+
#define FSL_FEATURE_PORT_HAS_PULL_SELECTION (1)
56+
/* @brief Has pull resistor enable (register bit PCR[PE]). */
57+
#define FSL_FEATURE_PORT_HAS_PULL_ENABLE (1)
58+
/* @brief Has slew rate control (register bit PCR[SRE]). */
59+
#define FSL_FEATURE_PORT_HAS_SLEW_RATE (0)
60+
/* @brief Has passive filter (register bit field PCR[PFE]). */
61+
#define FSL_FEATURE_PORT_HAS_PASSIVE_FILTER (1)
62+
/* @brief Has drive strength control (register bit PCR[DSE]). */
63+
#define FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH (1)
64+
/* @brief Has separate drive strength register (HDRVE). */
65+
#define FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH_REGISTER (0)
66+
/* @brief Has glitch filter (register IOFLT). */
67+
#define FSL_FEATURE_PORT_HAS_GLITCH_FILTER (0)
68+
/* @brief Defines width of PCR[MUX] field. */
69+
#define FSL_FEATURE_PORT_PCR_MUX_WIDTH (3)
70+
/* @brief Has dedicated interrupt vector. */
71+
#define FSL_FEATURE_PORT_HAS_INTERRUPT_VECTOR (1)
72+
/* @brief Has multiple pin IRQ configuration (register GICLR and GICHR). */
73+
#define FSL_FEATURE_PORT_HAS_MULTIPLE_IRQ_CONFIG (1)
74+
/* @brief Defines whether PCR[IRQC] bit-field has flag states. */
75+
#define FSL_FEATURE_PORT_HAS_IRQC_FLAG (0)
76+
/* @brief Defines whether PCR[IRQC] bit-field has trigger states. */
77+
#define FSL_FEATURE_PORT_HAS_IRQC_TRIGGER (0)
78+
79+
/* GPIO module features */
80+
81+
/* @brief Has GPIO attribute checker register (GACR). */
82+
#define FSL_FEATURE_GPIO_HAS_ATTRIBUTE_CHECKER (0)
83+
84+
/* LPUART module features */
85+
86+
/* @brief Has receive FIFO overflow detection (bit field CFIFO[RXOFE]). */
87+
#define FSL_FEATURE_LPUART_HAS_IRQ_EXTENDED_FUNCTIONS (0)
88+
/* @brief Has low power features (can be enabled in wait mode via register bit C1[DOZEEN] or CTRL[DOZEEN] if the registers are 32-bit wide). */
89+
#define FSL_FEATURE_LPUART_HAS_LOW_POWER_UART_SUPPORT (1)
90+
/* @brief Has extended data register ED (or extra flags in the DATA register if the registers are 32-bit wide). */
91+
#define FSL_FEATURE_LPUART_HAS_EXTENDED_DATA_REGISTER_FLAGS (1)
92+
/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */
93+
#define FSL_FEATURE_LPUART_HAS_FIFO (1)
94+
/* @brief Has 32-bit register MODIR */
95+
#define FSL_FEATURE_LPUART_HAS_MODIR (1)
96+
/* @brief Hardware flow control (RTS, CTS) is supported. */
97+
#define FSL_FEATURE_LPUART_HAS_MODEM_SUPPORT (1)
98+
/* @brief Infrared (modulation) is supported. */
99+
#define FSL_FEATURE_LPUART_HAS_IR_SUPPORT (1)
100+
/* @brief 2 bits long stop bit is available. */
101+
#define FSL_FEATURE_LPUART_HAS_STOP_BIT_CONFIG_SUPPORT (1)
102+
/* @brief If 10-bit mode is supported. */
103+
#define FSL_FEATURE_LPUART_HAS_10BIT_DATA_SUPPORT (1)
104+
/* @brief If 7-bit mode is supported. */
105+
#define FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT (1)
106+
/* @brief Baud rate fine adjustment is available. */
107+
#define FSL_FEATURE_LPUART_HAS_BAUD_RATE_FINE_ADJUST_SUPPORT (0)
108+
/* @brief Baud rate oversampling is available (has bit fields C4[OSR], C5[BOTHEDGE], C5[RESYNCDIS] or BAUD[OSR], BAUD[BOTHEDGE], BAUD[RESYNCDIS] if the registers are 32-bit wide). */
109+
#define FSL_FEATURE_LPUART_HAS_BAUD_RATE_OVER_SAMPLING_SUPPORT (1)
110+
/* @brief Baud rate oversampling is available. */
111+
#define FSL_FEATURE_LPUART_HAS_RX_RESYNC_SUPPORT (1)
112+
/* @brief Baud rate oversampling is available. */
113+
#define FSL_FEATURE_LPUART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (1)
114+
/* @brief Peripheral type. */
115+
#define FSL_FEATURE_LPUART_IS_SCI (1)
116+
/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */
117+
#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (4)
118+
/* @brief Supports two match addresses to filter incoming frames. */
119+
#define FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING (1)
120+
/* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */
121+
#define FSL_FEATURE_LPUART_HAS_DMA_ENABLE (1)
122+
/* @brief Has transmitter/receiver DMA select bits C4[TDMAS]/C4[RDMAS], resp. C5[TDMAS]/C5[RDMAS] if IS_SCI = 0. */
123+
#define FSL_FEATURE_LPUART_HAS_DMA_SELECT (0)
124+
/* @brief Data character bit order selection is supported (bit field S2[MSBF] or STAT[MSBF] if the registers are 32-bit wide). */
125+
#define FSL_FEATURE_LPUART_HAS_BIT_ORDER_SELECT (1)
126+
/* @brief Has smart card (ISO7816 protocol) support and no improved smart card support. */
127+
#define FSL_FEATURE_LPUART_HAS_SMART_CARD_SUPPORT (0)
128+
/* @brief Has improved smart card (ISO7816 protocol) support. */
129+
#define FSL_FEATURE_LPUART_HAS_IMPROVED_SMART_CARD_SUPPORT (0)
130+
/* @brief Has local operation network (CEA709.1-B protocol) support. */
131+
#define FSL_FEATURE_LPUART_HAS_LOCAL_OPERATION_NETWORK_SUPPORT (0)
132+
/* @brief Has 32-bit registers (BAUD, STAT, CTRL, DATA, MATCH, MODIR) instead of 8-bit (BDH, BDL, C1, S1, D, etc.). */
133+
#define FSL_FEATURE_LPUART_HAS_32BIT_REGISTERS (1)
134+
/* @brief Lin break detect available (has bit BAUD[LBKDIE]). */
135+
#define FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT (1)
136+
/* @brief UART stops in Wait mode available (has bit C1[UARTSWAI]). */
137+
#define FSL_FEATURE_LPUART_HAS_WAIT_MODE_OPERATION (0)
138+
/* @brief Has separate DMA RX and TX requests. */
139+
#define FSL_FEATURE_LPUART_HAS_SEPARATE_DMA_RX_TX_REQn(x) (0)
140+
/* @brief Has separate RX and TX interrupts. */
141+
#define FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ (0)
142+
/* @brief Has LPAURT_PARAM. */
143+
#define FSL_FEATURE_LPUART_HAS_PARAM (1)
144+
/* @brief Has LPUART_VERID. */
145+
#define FSL_FEATURE_LPUART_HAS_VERID (1)
146+
/* @brief Has LPUART_GLOBAL. */
147+
#define FSL_FEATURE_LPUART_HAS_GLOBAL (1)
148+
/* @brief Has LPUART_PINCFG. */
149+
#define FSL_FEATURE_LPUART_HAS_PINCFG (1)
150+
151+
/* LPI2C module features */
152+
153+
/* @brief Has separate DMA RX and TX requests. */
154+
#define FSL_FEATURE_LPI2C_HAS_SEPARATE_DMA_RX_TX_REQn(x) (1)
155+
/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */
156+
#define FSL_FEATURE_LPI2C_FIFO_SIZEn(x) (4)
157+
158+
/* LPSPI module features */
159+
160+
/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */
161+
#define FSL_FEATURE_LPSPI_FIFO_SIZEn(x) (4)
162+
/* @brief Has separate DMA RX and TX requests. */
163+
#define FSL_FEATURE_LPSPI_HAS_SEPARATE_DMA_RX_TX_REQn(x) (1)
164+
/* @brief Has CCR1 (related to existence of registers CCR1). */
165+
#define FSL_FEATURE_LPSPI_HAS_CCR1 (0)
166+
167+
/* LMEM module features */
168+
169+
/* @brief Has process identifier support. */
170+
#define FSL_FEATURE_LMEM_HAS_SYSTEMBUS_CACHE (0)
171+
/* @brief Has L1 cache. */
172+
#define FSL_FEATURE_HAS_L1CACHE (1)
173+
/* @brief L1 ICACHE line size in byte. */
174+
#define FSL_FEATURE_L1ICACHE_LINESIZE_BYTE (16)
175+
/* @brief L1 DCACHE line size in byte. */
176+
#define FSL_FEATURE_L1DCACHE_LINESIZE_BYTE (16)
177+
178+
/* FTM module features */
179+
180+
/* @brief Number of channels. */
181+
#define FSL_FEATURE_FTM_CHANNEL_COUNTn(x) (8)
182+
/* @brief Has counter reset by the selected input capture event (register bits C0SC[ICRST], C1SC[ICRST], ...). */
183+
#define FSL_FEATURE_FTM_HAS_COUNTER_RESET_BY_CAPTURE_EVENT (1)
184+
/* @brief Has extended deadtime value. */
185+
#define FSL_FEATURE_FTM_HAS_EXTENDED_DEADTIME_VALUE (1)
186+
/* @brief Enable pwm output for the module. */
187+
#define FSL_FEATURE_FTM_HAS_ENABLE_PWM_OUTPUT (1)
188+
/* @brief Has half-cycle reload for the module. */
189+
#define FSL_FEATURE_FTM_HAS_HALFCYCLE_RELOAD (1)
190+
/* @brief Has reload interrupt. */
191+
#define FSL_FEATURE_FTM_HAS_RELOAD_INTERRUPT (1)
192+
/* @brief Has reload initialization trigger. */
193+
#define FSL_FEATURE_FTM_HAS_RELOAD_INITIALIZATION_TRIGGER (1)
194+
/* @brief Has DMA support, bitfield CnSC[DMA]. */
195+
#define FSL_FEATURE_FTM_HAS_DMA_SUPPORT (1)
196+
/* @brief If channel 6 is used to generate channel trigger, bitfield EXTTRIG[CH6TRIG]. */
197+
#define FSL_FEATURE_FTM_HAS_CHANNEL6_TRIGGER (1)
198+
/* @brief If channel 7 is used to generate channel trigger, bitfield EXTTRIG[CH7TRIG]. */
199+
#define FSL_FEATURE_FTM_HAS_CHANNEL7_TRIGGER (1)
200+
/* @brief If instance has only TPM function. */
201+
#define FSL_FEATURE_FTM_IS_TPM_ONLY_INSTANCEn(x) (0)
202+
/* @brief Has frequency of the reload opportunities, bitfield CONF[LDFQ]. */
203+
#define FSL_FEATURE_FTM_HAS_CONF_LDFQ_BIT (1)
204+
205+
/* FLEXCAN module features */
206+
207+
/* @brief Message buffer size */
208+
#define FSL_FEATURE_FLEXCAN_HAS_MESSAGE_BUFFER_MAX_NUMBERn(x) \
209+
(((x) == CAN0) ? (32) : \
210+
(((x) == CAN1) ? (32) : \
211+
(((x) == CAN2) ? (32) : (-1))))
212+
/* @brief Has doze mode support (register bit field MCR[DOZE]). */
213+
#define FSL_FEATURE_FLEXCAN_HAS_DOZE_MODE_SUPPORT (0)
214+
/* @brief Insatnce has doze mode support (register bit field MCR[DOZE]). */
215+
#define FSL_FEATURE_FLEXCAN_INSTANCE_HAS_DOZE_MODE_SUPPORTn(x) (0)
216+
/* @brief Has a glitch filter on the receive pin (register bit field MCR[WAKSRC]). */
217+
#define FSL_FEATURE_FLEXCAN_HAS_GLITCH_FILTER (0)
218+
/* @brief Has extended interrupt mask and flag register (register IMASK2, IFLAG2). */
219+
#define FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER (0)
220+
/* @brief Instance has extended bit timing register (register CBT). */
221+
#define FSL_FEATURE_FLEXCAN_INSTANCE_HAS_EXTENDED_TIMING_REGISTERn(x) (1)
222+
/* @brief Has a receive FIFO DMA feature (register bit field MCR[DMA]). */
223+
#define FSL_FEATURE_FLEXCAN_HAS_RX_FIFO_DMA (1)
224+
/* @brief Instance has a receive FIFO DMA feature (register bit field MCR[DMA]). */
225+
#define FSL_FEATURE_FLEXCAN_INSTANCE_HAS_RX_FIFO_DMAn(x) (1)
226+
/* @brief Remove CAN Engine Clock Source Selection from unsupported part. */
227+
#define FSL_FEATURE_FLEXCAN_SUPPORT_ENGINE_CLK_SEL_REMOVE (0)
228+
/* @brief Instance remove CAN Engine Clock Source Selection from unsupported part. */
229+
#define FSL_FEATURE_FLEXCAN_INSTANCE_SUPPORT_ENGINE_CLK_SEL_REMOVEn(x) (0)
230+
/* @brief Has CAN with Flexible Data rate (CAN FD) protocol. */
231+
#define FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE (1)
232+
/* @brief CAN instance support Flexible Data rate (CAN FD) protocol. */
233+
#define FSL_FEATURE_FLEXCAN_INSTANCE_HAS_FLEXIBLE_DATA_RATEn(x) \
234+
(((x) == CAN0) ? (1) : \
235+
(((x) == CAN1) ? (1) : \
236+
(((x) == CAN2) ? (1) : (0))))
237+
/* @brief Has memory error control (register MECR). */
238+
#define FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_CONTROL (0)
239+
/* @brief Has enhanced bit timing register (register EPRS, ENCBT, EDCBT and ETDC). */
240+
#define FSL_FEATURE_FLEXCAN_HAS_ENHANCED_BIT_TIMING_REG (0)
241+
/* @brief Has Pretended Networking mode support. */
242+
#define FSL_FEATURE_FLEXCAN_HAS_PN_MODE (1)
243+
/* @brief Has Enhanced Rx FIFO. */
244+
#define FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO (0)
245+
/* @brief Does not support Supervisor Mode (bitfield MCR[SUPV]. */
246+
#define FSL_FEATURE_FLEXCAN_HAS_NO_SUPV_SUPPORT (1)
247+
248+
/* WDOG module features */
249+
250+
/* @brief Watchdog is available. */
251+
#define FSL_FEATURE_WDOG_HAS_WATCHDOG (1)
252+
/* @brief WDOG_CNT can be 32-bit written. */
253+
#define FSL_FEATURE_WDOG_HAS_32BIT_ACCESS (1)
254+
255+
/* RTC module features */
256+
257+
/* @brief Has wakeup pin. */
258+
#define FSL_FEATURE_RTC_HAS_WAKEUP_PIN (0)
259+
/* @brief Has wakeup pin selection (bit field CR[WPS]). */
260+
#define FSL_FEATURE_RTC_HAS_WAKEUP_PIN_SELECTION (0)
261+
/* @brief Has low power features (registers MER, MCLR and MCHR). */
262+
#define FSL_FEATURE_RTC_HAS_MONOTONIC (0)
263+
/* @brief Has read/write access control (registers WAR and RAR). */
264+
#define FSL_FEATURE_RTC_HAS_ACCESS_CONTROL (0)
265+
/* @brief Has security features (registers TTSR, MER, MCLR and MCHR). */
266+
#define FSL_FEATURE_RTC_HAS_SECURITY (0)
267+
/* @brief Has RTC_CLKIN available. */
268+
#define FSL_FEATURE_RTC_HAS_RTC_CLKIN (1)
269+
/* @brief Has prescaler adjust for LPO. */
270+
#define FSL_FEATURE_RTC_HAS_LPO_ADJUST (1)
271+
/* @brief Has Clock Pin Enable field. */
272+
#define FSL_FEATURE_RTC_HAS_CPE (1)
273+
/* @brief Has Timer Seconds Interrupt Configuration field. */
274+
#define FSL_FEATURE_RTC_HAS_TSIC (1)
275+
/* @brief Has OSC capacitor setting RTC_CR[SC2P ~ SC16P] */
276+
#define FSL_FEATURE_RTC_HAS_OSC_SCXP (0)
277+
/* @brief Has Tamper Interrupt Register (register TIR). */
278+
#define FSL_FEATURE_RTC_HAS_TIR (0)
279+
/* @brief Has Tamper Pin Interrupt Enable (bitfield TIR[TPIE]). */
280+
#define FSL_FEATURE_RTC_HAS_TIR_TPIE (0)
281+
/* @brief Has Security Interrupt Enable (bitfield TIR[SIE]). */
282+
#define FSL_FEATURE_RTC_HAS_TIR_SIE (0)
283+
/* @brief Has Loss of Clock Interrupt Enable (bitfield TIR[LCIE]). */
284+
#define FSL_FEATURE_RTC_HAS_TIR_LCIE (0)
285+
/* @brief Has Tamper Interrupt Detect Flag (bitfield SR[TIDF]). */
286+
#define FSL_FEATURE_RTC_HAS_SR_TIDF (0)
287+
/* @brief Has Tamper Detect Register (register TDR). */
288+
#define FSL_FEATURE_RTC_HAS_TDR (0)
289+
/* @brief Has Tamper Pin Flag (bitfield TDR[TPF]). */
290+
#define FSL_FEATURE_RTC_HAS_TDR_TPF (0)
291+
/* @brief Has Security Tamper Flag (bitfield TDR[STF]). */
292+
#define FSL_FEATURE_RTC_HAS_TDR_STF (0)
293+
/* @brief Has Loss of Clock Tamper Flag (bitfield TDR[LCTF]). */
294+
#define FSL_FEATURE_RTC_HAS_TDR_LCTF (0)
295+
/* @brief Has Tamper Time Seconds Register (register TTSR). */
296+
#define FSL_FEATURE_RTC_HAS_TTSR (0)
297+
/* @brief Has Pin Configuration Register (register PCR). */
298+
#define FSL_FEATURE_RTC_HAS_PCR (0)
299+
/* @brief Has Oscillator Enable(bitfield CR[OSCE]). */
300+
#define FSL_FEATURE_RTC_HAS_NO_CR_OSCE (1)
301+
302+
/* ADC12 module features */
303+
304+
/* @brief Has DMA support (bit SC2[DMAEN]. */
305+
#define FSL_FEATURE_ADC12_HAS_DMA_SUPPORT (1)
306+
/* @brief Conversion control count (related to number of registers SC1n and Rn). */
307+
#define FSL_FEATURE_ADC12_CONVERSION_CONTROL_COUNT (32)
308+
309+
#endif /* _S32K148_FEATURES_H_ */

‎s32/mcux/devices/S32K148/device_CMSIS.cmake

+12
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,12 @@
1+
include_guard(GLOBAL)
2+
message("device_CMSIS component is included.")
3+
4+
target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE
5+
# nothing to build
6+
)
7+
8+
target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC
9+
${CMAKE_CURRENT_LIST_DIR}/.
10+
)
11+
12+
include(CMSIS_Include_core_cm)

‎s32/mcux/devices/S32K148/device_system.cmake

+10
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,10 @@
1+
include_guard(GLOBAL)
2+
message("device_system component is included.")
3+
4+
target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE
5+
# nothing to build
6+
)
7+
8+
target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC
9+
# nothing to include
10+
)

‎s32/mcux/devices/S32K148/drivers/driver_memory.cmake

+10
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,10 @@
1+
include_guard(GLOBAL)
2+
message("driver_memory component is included.")
3+
4+
target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE
5+
# nothing to build
6+
)
7+
8+
target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC
9+
${CMAKE_CURRENT_LIST_DIR}/.
10+
)

‎s32/mcux/devices/S32K148/drivers/driver_reset.cmake

+10
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,10 @@
1+
include_guard(GLOBAL)
2+
message("driver_reset component is included.")
3+
4+
target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE
5+
# nothing to build
6+
)
7+
8+
target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC
9+
${CMAKE_CURRENT_LIST_DIR}/.
10+
)

‎s32/mcux/devices/S32K148/drivers/fsl_clock.h

+12
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,12 @@
1+
/*
2+
* Copyright 2023 NXP
3+
*
4+
* SPDX-License-Identifier: BSD-3-Clause
5+
*/
6+
7+
#ifndef _FSL_CLOCK_H_
8+
#define _FSL_CLOCK_H_
9+
10+
#include "fsl_common.h"
11+
12+
#endif /* _FSL_CLOCK_H_ */

0 commit comments

Comments
 (0)