Update blue-crc submodule

wengwz · Aug 2, 2023 · 58d7f8d · 58d7f8d
1 parent 82d3d3c
commit 58d7f8d
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Showing 8 changed files with 28 additions and 153 deletions.
diff --git a/.gitmodules b/.gitmodules
@@ -1,3 +1,6 @@
 [submodule "lib/blue-wrapper"]
 	path = lib/blue-wrapper
 	url = https://github.com/wengwz/blue-wrapper.git
+[submodule "lib/blue-crc"]
+	path = lib/blue-crc
+	url = https://github.com/datenlord/blue-crc.git
diff --git a/lib/blue-crc b/lib/blue-crc
diff --git a/scripts/crc_ieee_32_256.json b/scripts/crc_ieee_32_256.json
@@ -0,0 +1,11 @@
+{
+    "crc_width": 32,
+    "axi_keep_width": 32,
+    "polynomial": "0x04C11DB7",
+    "init_value": "0xFFFFFFFF",
+    "final_xor": "0xFFFFFFFF",
+    "reverse_input": true,
+    "reverse_output": true,
+    "mem_file_prefix": "crc_tab",
+    "crc_mode": "CRC_MODE_SEND"
+}
diff --git a/src/includes/Utils.bsv b/src/includes/Utils.bsv
@@ -686,14 +686,14 @@ module mkSizedBramFifoToPipeOut#(
 
     FIFOF#(dType) fifo <- mkSizedBRAMFIFOF(depth);
     rule doEnq;
-        if (fifo.notFull) begin
-            fifo.enq(pipe.first);
-            pipe.deq;
-            $display("BramFifo enq ", fshow(pipe.first));
-        end
-        else begin
-            $display("BramFifo is Full");
-        end
+        //if (fifo.notFull) begin
+        fifo.enq(pipe.first);
+        pipe.deq;
+            // $display("BramFifo enq ", fshow(pipe.first));
+        // end
+        // else begin
+        //     $display("BramFifo is Full");
+        // end
     endrule
     return convertFifoToPipeOut(fifo);
 endmodule

diff --git a/syn/Makefile b/syn/Makefile
@@ -5,11 +5,12 @@ LOCALSRCDIR = $(ROOT_DIR)/src:$(ROOT_DIR)/src/includes
 LIB_CRC_DIR = $(ROOT_DIR)/lib/blue-crc/src
 LIB_WRAPPER_DIR = $(ROOT_DIR)/lib/blue-wrapper/src
 LIBSRCDIR = $(LIB_CRC_DIR):$(LIB_WRAPPER_DIR)
+CRC_TAB_SCRIPT = $(ROOT_DIR)/lib/blue-crc/scripts/gen_crc_tab.py
 
 PWD = $(shell pwd)
 VLOGDIR = generated
 OUTPUTDIR = output_ooc
-ONLYSYNTH = 0
+ONLYSYNTH = 1
 CLK = main_clock
 
 TARGET = RdmaUdpArpEthRxTx
@@ -23,7 +24,7 @@ export SYNTHONLY = $(ONLYSYNTH)
 export CLOCKS = $(CLK)
 
 table:
-	python3 $(LIB_CRC_DIR)/gen_crc_tab.py 32 256
+	python3 $(CRC_TAB_SCRIPT) $(SCRIPTS_DIR)/crc_ieee_32_256.json ./
 
 compile:
 	mkdir -p $(BUILDDIR)

diff --git a/test/bluesim/TestUdpReceiver.bsv b/test/bluesim/TestUdpReceiver.bsv
diff --git a/test/bluesim/TestUdpTransmitter.bsv b/test/bluesim/TestUdpTransmitter.bsv
diff --git a/test/cocotb/Makefile b/test/cocotb/Makefile
@@ -5,6 +5,7 @@ LOCALSRCDIR = $(ROOT_DIR)/src:$(ROOT_DIR)/src/includes
 LIB_CRC_DIR = $(ROOT_DIR)/lib/blue-crc/src
 LIB_WRAPPER_DIR = $(ROOT_DIR)/lib/blue-wrapper/src
 LIBSRCDIR = $(LIB_CRC_DIR):$(LIB_WRAPPER_DIR)
+CRC_TAB_SCRIPT = $(ROOT_DIR)/lib/blue-crc/scripts/gen_crc_tab.py
 
 TARGET = RdmaUdpIpEthRx
 FILE_PATH = $(ROOT_DIR)/src
@@ -15,7 +16,7 @@ VLOGDIR = verilog
 VLOG_FILE = $(VLOGDIR)/$(TOP).v
 
 table:
-	python3 $(LIB_CRC_DIR)/gen_crc_tab.py 32 256
+	python3 $(CRC_TAB_SCRIPT) $(SCRIPTS_DIR)/crc_ieee_32_256.json ./
 
 verilog:
 	mkdir -p $(BUILDDIR)