[ROCm][DSV4] Use aiter mHC pre/post as the default ROCm path#43950
[ROCm][DSV4] Use aiter mHC pre/post as the default ROCm path#43950Fangzhou-Ai wants to merge 1 commit into
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Re-enable the aiter multi-head-consensus (mHC) pre/post ops as the preferred ROCm path for DeepSeek V4. PR vllm-project#43679 added a tilelang fused post+pre mHC kernel and left a hook to switch back to the (faster) aiter mHC kernels once an aiter release with the sqrsum race-condition fix was available; this is that follow-up. Dispatch is now purely capability based (no new env knobs): aiter mHC pre/post -> tilelang fused post+pre -> torch/triton reference The aiter kernels are used whenever aiter is available on a supported ROCm device (``is_aiter_found_and_supported()``) and the hidden size is a multiple of 256; otherwise we fall back to the tilelang fused kernel, and finally to the torch/triton reference implementation. On CUDA the tilelang path is unchanged. The aiter mHC kernels require aiter >= 0.1.14, which contains the sqrsum race-condition fix in ``mhc_pre_gemm_sqrsum_kernel`` (ROCm/aiter@b639cb6); without it results are wrong at large token counts. AITER_BRANCH in docker/Dockerfile.rocm_base is bumped v0.1.13 -> v0.1.14. The unfused aiter path applies hc_post inline and returns no residual streams, so the deferred hc_post in DeepseekV4Model.forward and the MTP layer is gated on ``residual is not None`` rather than has_tilelang/is_cuda. Signed-off-by: Fangzhou Ai <fangzhou.ai@amd.com> Co-authored-by: Cursor <cursoragent@cursor.com>
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| ARG FA_BRANCH="0e60e394" | ||
| ARG FA_REPO="https://github.com/Dao-AILab/flash-attention.git" | ||
| ARG AITER_BRANCH="v0.1.13" | ||
| ARG AITER_BRANCH="v0.1.14" |
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There is release cadence for ROCm major lib version bumps.
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@Fangzhou-Ai on upstream we do not bump other dependencies version. So this PR will only be continued after aiter is upgraded.
Purpose
Re-enable the aiter multi-head-consensus (mHC) pre/post ops as the preferred ROCm path for DeepSeek V4. #43679 introduced the tilelang fused post+pre mHC kernel and explicitly left a hook to switch back to the (faster) aiter mHC kernels once an aiter release containing the
mhc_pre_gemm_sqrsum_kernelrace-condition fix was available. This is that follow-up.Dispatch / fallback path
Selection is purely capability based — no new env knobs:
is_aiter_found_and_supported(), i.e. ROCm + gfx9/MI3xx + aiter installed) and the hidden size is a multiple of 256 (kernel constraint).The unfused aiter path applies
hc_postinline and returns no residual streams, so the deferredhc_postinDeepseekV4Model.forwardand the MTP layer is gated onresidual is not Nonerather thanhas_tilelang/is_cuda.The aiter mHC kernels require aiter >= 0.1.14, which contains the sqrsum race-condition fix in
mhc_pre_gemm_sqrsum_kernel(ROCm/aiter@b639cb6); without it results are wrong at large token counts.AITER_BRANCHindocker/Dockerfile.rocm_baseis bumpedv0.1.13 -> v0.1.14.Not a duplicate
This is the aiter follow-up that #43679 (merged) explicitly deferred. A scan of open PRs (
mHC,deepseek v4 mhc aiter) shows the other ROCm DSv4 PRs cover unrelated areas (#42893 MI300X functional fixes, #41136 model enablement, #41451 MI300 support, #40909/#40892 AITER MLA decode, #42735 tilelang mHC-pre perf). None re-enables the aiter mHC pre/post path. No overlap.Test Plan
ROCm, 8x MI3xx,
DeepSeek-V4-Pro,tp=8,--kv-cache-dtype fp8,--moe-backend triton_unfused,--compilation-config '{"mode":3,"cudagraph_mode":"FULL_AND_PIECEWISE"}'.lm_eval(--num_fewshot 20) on the aiter mHC path.vllm bench serve(random,--random-range-ratio 0.8,--num-warmups C*2,--num-prompts C*5) comparing aiter mHC vs the tilelang fused kernel at 1k/1k and 8k/1k, concurrency 4 and 64.Test Result
Accuracy — gsm8k (num_fewshot=20, aiter mHC, no MTP)
Within #43679's accuracy gate (
0.95 ± 0.01; tilelang baseline there: 0.9553 / 0.9560). A 20-shot run was used specifically to stress large token counts and confirm the aiter v0.1.14 sqrsum fix (v0.1.13 regressed badly under that stress).Performance — aiter mHC vs tilelang fused (output tok/s, higher is better)
1k/1k (input 1024 / output 1024):
8k/1k (input 8192 / output 1024):
aiter mHC is consistently faster than the tilelang fused kernel across both workloads and concurrencies (+4.7% to +7.2% throughput, lower TPOT). The tilelang baseline matched #43679's published numbers.
Path verification: with aiter present, workers log
[aiter] import [module_mhc] .../module_mhc.soand generation is correct; forcing the fallbacks (no aiter / no tilelang) exercises the tilelang and torch/triton paths.pre-commit run --files(ruff, ruff-format, mypy, typos, SPDX, ...) passes on all changed files.AI assistance (Cursor) was used to prepare this change; the human submitter has reviewed every changed line and run the tests above.
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