refactor : fix linting issues in concat controller

src/rtl/common/memory_valid.v

@@ -1,58 +1,43 @@
 /* This memory module is used in the synchronous fifo which is used for checking validity of data.
 It checks whether the correct data is read from memory or not */
-module memory_valid
-    ( 
-      wr_clk,  
-      wr_rst_n,  
-      rd_clk,  
-      rd_rst_n,  
-      wdata,  
-      waddr,  
-      raddr,  
-      wr_en,
-      rd_en,
-      rdata,
-      valid,
-      empty_flag,
-      full_flag
-     );
+module memory_valid # (
+    parameter DATA_WIDTH = 8,
+    parameter ADDR_WIDTH = 8,
+    parameter RAM_DEPTH = (1 << ADDR_WIDTH))
+    (
+    input wr_clk,
+    input rd_clk,
+    input [DATA_WIDTH-1:0] wdata,
+    input [ADDR_WIDTH-1:0] waddr,
+    input [ADDR_WIDTH-1:0] raddr,
+    input wr_en,
+    input rd_en,
+    input empty_flag,
+    input full_flag,
+    output [DATA_WIDTH-1:0] rdata,
+    output valid
+    );
 
-parameter DATA_WIDTH = 8;
-parameter ADDR_WIDTH = 8;
-parameter RAM_DEPTH = (1 << ADDR_WIDTH);
+    reg [DATA_WIDTH-1:0] mem [RAM_DEPTH-1:0];
+    reg [DATA_WIDTH-1:0] rdata = 0;
+    reg dv = 0;
 
-input wr_rst_n; 
-input wr_clk; 
-input rd_rst_n; 
-input rd_clk;
-input [DATA_WIDTH-1:0] wdata; 
-input [ADDR_WIDTH-1:0] waddr; 
-input [ADDR_WIDTH-1:0] raddr; 
-input wr_en;
-input rd_en;
-input empty_flag;
-input full_flag;
-output [DATA_WIDTH-1:0] rdata; 
-output valid;
+    assign valid = dv;
 
-reg [DATA_WIDTH-1:0] mem [RAM_DEPTH-1:0];
-reg [DATA_WIDTH-1:0] rdata = 0;
-reg dv = 0;
+    always @(posedge rd_clk) begin
+        if(rd_en & (!empty_flag)) begin
+            rdata <= mem [raddr];
+            dv <= 1'b1;
+        end
+        else begin
+            rdata <= rdata;
+            dv <= 1'b0;
+        end
+    end
 
-assign valid = dv;
-
-always @(posedge rd_clk)
-    if(rd_en & (!empty_flag)) begin
-    rdata <= mem [raddr];
-    dv <= 1'b1;
-    end 
-    else begin
-    rdata <= rdata;
-    dv <= 1'b0;
-end
-
-always @(posedge wr_clk)
-    if(wr_en & (!full_flag))  
-        mem[waddr] <= wdata;  
+    always @(posedge wr_clk) begin
+        if(wr_en & (!full_flag))
+            mem[waddr] <= wdata;
+    end
 
 endmodule

src/rtl/concat/concat_controller.v

@@ -47,7 +47,7 @@ module concat_controller #
   always @(posedge i_clk ) begin
     if (i_rst) begin
       concat_read_enable        <= 1'b0;
-      o_concat_dv     <= 1'b0;
+      o_concat_dv               <= 1'b0;
       o_concat_data             <= 32'd0;
       total_words_remaining     <= 32'd0;
       buf_valid                 <= 1'b0;
@@ -74,28 +74,28 @@ module concat_controller #
         READ: begin
 
           if ((total_words_remaining == 0))
-             state = DONE;
-          else begin  
+             state <= DONE;
+          else begin
           if (!concat_fifo_empty && !quant_op_fifo_full) begin
             concat_read_enable <= 1'b1;
             buf_valid          <= 1'b1;
             state              <= WRITE;
           end
-          else state <= READ;
+          else state           <= READ;
           end
         end
 
 
         WRITE: begin
           concat_read_enable <= 1'b0;
           if ((total_words_remaining == 0))
-             state = DONE;
+             state <= DONE;
           else begin
             if (i_dram_fifo_dv && (total_words_remaining != 0)) begin
               o_concat_data         <= i_concat_data;
               o_concat_dv           <= 1'b1;
               total_words_remaining <= total_words_remaining - 32;
-              state <= READ ;
+              state                 <= READ ;
             end
             else state <= WRITE;
           end
@@ -104,7 +104,7 @@ module concat_controller #
         // --------------------------
         DONE: begin
           o_done <= 1'b1;
-          state <= IDLE;
+          state  <= IDLE;
         end
 
       endcase