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Modifying comments to reflect new changes to single and dual port ram primitives
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2 files changed

+7
-7
lines changed

2 files changed

+7
-7
lines changed

parmys/third_party/vtr_flow/primitives.v

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -268,7 +268,7 @@ module single_port_ram #(
268268
if(we) begin
269269
Mem[addr] <= data;
270270
end
271-
out <= Mem[addr]; //New data read-during write behaviour (blocking assignments)
271+
out <= Mem[addr]; //Old data read-first behaviour (non-blocking assignments)
272272
end
273273

274274
endmodule // single_port_RAM
@@ -316,14 +316,14 @@ module dual_port_ram #(
316316
if(we1) begin
317317
Mem[addr1] <= data1;
318318
end
319-
out1 <= Mem[addr1]; //New data read-during write behaviour (blocking assignments)
319+
out1 <= Mem[addr1]; //Old data read-first behaviour (non-blocking assignments)
320320
end
321321

322322
always@(posedge clk) begin //Port 2
323323
if(we2) begin
324324
Mem[addr2] <= data2;
325325
end
326-
out2 <= Mem[addr2]; //New data read-during write behaviour (blocking assignments)
326+
out2 <= Mem[addr2]; //Old data read-first behaviour (non-blocking assignments)
327327
end
328328

329329
endmodule // dual_port_ram

vtr_flow/primitives.v

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -268,7 +268,7 @@ module single_port_ram #(
268268
if(we) begin
269269
Mem[addr] <= data;
270270
end
271-
out <= Mem[addr]; //New data read-during write behaviour (blocking assignments)
271+
out <= Mem[addr]; //Old data read-first behaviour (non-blocking assignments)
272272
end
273273

274274
endmodule // single_port_RAM
@@ -314,16 +314,16 @@ module dual_port_ram #(
314314

315315
always@(posedge clk) begin //Port 1
316316
if(we1) begin
317-
Mem[addr1] = data1;
317+
Mem[addr1] <= data1;
318318
end
319-
out1 = Mem[addr1]; //New data read-during write behaviour (blocking assignments)
319+
out1 <= Mem[addr1]; //Old data read-first behaviour (non-blocking assignments)
320320
end
321321

322322
always@(posedge clk) begin //Port 2
323323
if(we2) begin
324324
Mem[addr2] <= data2;
325325
end
326-
out2 <= Mem[addr2]; //New data read-during write behaviour (blocking assignments)
326+
out2 <= Mem[addr2]; //Old data read-first behaviour (non-blocking assignments)
327327
end
328328

329329
endmodule // dual_port_ram

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