MPSOC

DCLS Project File List

Source Files:

1. DCLS_Top.v - Main dual-core lockstep top module
2. RISC_V_Core_Mockup.v - Simplified RISC-V core for testing (replace with actual)
3. memory_unit_Mockup.v - Simple memory unit for testing (replace with actual)

Testbench Files:

4. tb_DCLS_Top.v - Comprehensive testbench with 7 test scenarios

Documentation:

5. README_DCLS_Modules.md - Main documentation and usage guide
6. Implementation_Notes.md - Important issues and integration notes
7. File_List.txt - This file

Scripts:

8. run_dcls_tb.tcl - Vivado batch mode simulation script
9. run_dcls_tb.do - ModelSim/QuestaSim simulation script

Total: 9 files

Note: Replace the mockup modules (files 2 and 3) with your actual RISC-V processor and memory unit implementations for the complete system.