Added JTAG-to-memory-mapped bus (TL & AXI4) master bridge. #224
Conversation
|
@milovanovic I'd like to help get this merged but I'm a little unsure of the best approach. Changes to chisel-testers and updating scalatest has created a lot of errors. I have fixed these locally. I could push them as a PR to your master branch, or maybe there's a better way. Do you have any ideas. |
|
Thanks @chick for getting involved. Whatever you think is the best approach we'll do. I invited you as a collaborator to local forks so if it's easier, take the shortcut. Otherwise just place a PR to the master branch. The bigger problem I see is that the current |
|
Thanks, I'm trying to figure out the best way to get my updates, I just
created a PR that you can ignore for the moment, there's some conflict I'm
trying to figure
out. Thanks for adding me.
And yes, I'd love to get the rocket-dsptools fixed, though I don't quite
know what to do there yet, I've been talking to Jack at SiFive about what
the options are
Chick Markley
Staff Programmer -- Adept Lab
University of California, Berkeley
583-2 Soda Hall, Berkeley, CA 94720-1776
***@***.***
…On Tue, Apr 20, 2021 at 9:54 AM Vladimir Milovanović < ***@***.***> wrote:
Thanks @chick <https://github.com/chick> for getting involved. Whatever
you think is the best approach we'll do. I invited you as a collaborator to
local forks so if it's easier, take the shortcut. Otherwise just place a PR
to the master branch. The bigger problem I see is that the current
rocket-dsptools subproject is not in CI, it doesn't build locally,
neither its tests pass. Migration from Travis to Actions is perhaps a good
time to add fixed rocket-dsptools into it also. If the rocket gets
settled on your side, I believe we'll find a way to polish the JTAG2MM and
integrate it.
—
You are receiving this because you were mentioned.
Reply to this email directly, view it on GitHub
<#224 (comment)>, or
unsubscribe
<https://github.com/notifications/unsubscribe-auth/AAHBMV5WSCGROX3NQ243GDDTJWWUDANCNFSM4ZWBFYPA>
.
|
- Driver now uses iotesters compatibility stuff - Tests change to used last scala tests - Add `Any` prefix to scalatest class names - Matchers import has changed - `withClockAndReset` moved out of experimental package
Compatibility fixes for 3.5
|
@milovanovic This looks good, and it seems to have all my changes. Any reasons not to merge it now? |
|
this pr is crashed by the up to dated RC |
|
Should fix in #231 |
3 participants
This adds a JTAG-to-memory-mapped bus master bridge, right now only for TL and AXI4, but could be potentially extended to other buses like AHB or APB. The main idea is to be able to test (in hardware) memory-mapped peripherals (e.g., a
DspBlock) by reading from and writing to their status and configuration registers without having to invoke a complete processor core like Rocket. Portions of the code are reused from chisel-jtag and/or Rocket Chip JTAG. The same PR is recently opened against testchipip. Feel free to give improvement suggestions and to change the license to whatever you believe is the most suitable one.