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Move emitRef from Verilog to backend #487

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Move emitRef from Verilog to backend #487

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b14b1d2
Move emitDef from Verilog to backend;
Aug 10, 2015
cdec7a0
Put the first nameAll back in
Aug 11, 2015
91bf227
Merge branch 'master' into nameDeclarations
Jan 20, 2016
eb1865e
Merge branch 'master' into nameDeclarations
Mar 6, 2016
ad9ea28
Update MultiClockSuite_Comp_1.v success code.
ucbjrl Aug 13, 2015
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6 changes: 6 additions & 0 deletions src/main/scala/Backend.scala
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Original file line number Diff line number Diff line change
Expand Up @@ -204,6 +204,8 @@ class Backend extends FileSystemUtilities{
comp dfs {
case reg: Reg if reg.name.isEmpty =>
reg setName "R" + reg.component.nextIndex
case clk: Clock if clk.name == "" =>
clk setName "C" + clk.component.nextIndex
case mem: Mem[_] if mem.name.isEmpty =>
mem setName "T" + mem.component.nextIndex
case node: Node if !node.isTypeNode && node.name.isEmpty && node.compOpt != None =>
Expand All @@ -221,6 +223,8 @@ class Backend extends FileSystemUtilities{
comp dfs {
case reg: Reg =>
reg setName namespace.getUniqueName(reg.name)
case clk: Clock =>
clk setName namespace.getUniqueName(clk.name)
case mem: Mem[_] =>
mem setName namespace.getUniqueName(mem.name)
case node: Node if !node.isTypeNode && !node.isLit && !node.isIo => {
Expand Down Expand Up @@ -266,6 +270,8 @@ class Backend extends FileSystemUtilities{
node.name
case _: Reg =>
if (node.named) node.name else "R" + node.emitIndex
case _: Clock =>
if (node.named) node.name else "C" + node.emitIndex
case _ =>
if (node.named) node.name else "T" + node.emitIndex
}
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4 changes: 1 addition & 3 deletions src/main/scala/Verilog.scala
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Expand Up @@ -100,10 +100,8 @@ class VerilogBackend extends Backend {
override def emitRef(node: Node): String = {
node match {
case x: Literal => emitLit(x.value, x.needWidth())
case _: Reg =>
if (node.name != "") node.name else "R" + node.emitIndex
case _ =>
if (node.name != "") node.name else "T" + node.emitIndex
super.emitRef(node)
}
}

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8 changes: 4 additions & 4 deletions src/test/resources/MultiClockSuite_Comp_1.v
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Original file line number Diff line number Diff line change
@@ -1,4 +1,4 @@
module MultiClockSuite_ClockedSubComp_1(input T0,
module MultiClockSuite_ClockedSubComp_1(input C0,
input io_ready,
output io_valid
);
Expand All @@ -17,12 +17,12 @@ module MultiClockSuite_ClockedSubComp_1(input T0,

assign io_valid = stored;

always @(posedge T0) begin
always @(posedge C0) begin
stored <= io_ready;
end
endmodule

module MultiClockSuite_Comp_1(input T0,
module MultiClockSuite_Comp_1(input C0,
input io_data0,
input io_data1,
output io_result
Expand All @@ -34,7 +34,7 @@ module MultiClockSuite_Comp_1(input T0,

assign T0 = io_data0 & io_data1;
assign io_result = sub_io_valid;
MultiClockSuite_ClockedSubComp_1 sub(.T0(T0),
MultiClockSuite_ClockedSubComp_1 sub(.C0(C0),
.io_ready( T0 ),
.io_valid( sub_io_valid )
);
Expand Down