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Merged
merged 1 commit into from
Sep 11, 2025
Merged

Experimental chisel7 support #2293

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44 changes: 44 additions & 0 deletions .github/workflows/chipyard-chisel7.yml
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Original file line number Diff line number Diff line change
@@ -0,0 +1,44 @@
name: chipyard-chisel7

on:
pull_request:
branches:
- main
- '1.[0-9]*.x'
workflow_dispatch:

defaults:
run:
shell: bash -leo pipefail {0}

jobs:
chisel7-firrtl:
name: chisel7-firrtl
runs-on: ubuntu-latest
steps:
- name: Checkout
uses: actions/checkout@v4

- name: Install DTC (device-tree-compiler)
run: |
sudo apt-get update
sudo apt-get install -y device-tree-compiler

- name: Set up JDK 17 (Temurin)
uses: actions/setup-java@v4
with:
distribution: 'temurin'
java-version: '17'
cache: 'sbt'

- name: Init submodules (saturn only)
run: |
scripts/init-submodules-no-riscv-tools-nolog.sh --saturn

- name: Run firrtl target with Chisel 7
env:
USE_CHISEL7: "1"
run: |
cd sims/verilator
make firrtl

67 changes: 55 additions & 12 deletions build.sbt
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Original file line number Diff line number Diff line change
@@ -1,6 +1,7 @@
import Tests._

val chisel6Version = "6.7.0"
val chisel7Version = "7.0.0-RC4"
val chiselTestVersion = "6.0.0"
val scalaVersionFromChisel = "2.13.16"

Expand Down Expand Up @@ -92,12 +93,17 @@ lazy val chisel6Settings = Seq(
libraryDependencies ++= Seq("org.chipsalliance" %% "chisel" % chisel6Version),
addCompilerPlugin("org.chipsalliance" % "chisel-plugin" % chisel6Version cross CrossVersion.full)
)
lazy val chisel7Settings = Seq(
libraryDependencies ++= Seq("org.chipsalliance" %% "chisel" % chisel7Version),
addCompilerPlugin("org.chipsalliance" % "chisel-plugin" % chisel7Version cross CrossVersion.full)
)
lazy val chisel3Settings = Seq(
libraryDependencies ++= Seq("edu.berkeley.cs" %% "chisel3" % chisel3Version),
addCompilerPlugin("edu.berkeley.cs" % "chisel3-plugin" % chisel3Version cross CrossVersion.full)
)

lazy val chiselSettings = chisel6Settings ++ Seq(
// Select Chisel 7 when USE_CHISEL7 is set in the environment; default to Chisel 6.
lazy val chiselSettings = (if (sys.env.contains("USE_CHISEL7")) chisel7Settings else chisel6Settings) ++ Seq(
libraryDependencies ++= Seq(
"org.apache.commons" % "commons-lang3" % "3.12.0",
"org.apache.commons" % "commons-text" % "1.9"
Expand All @@ -115,11 +121,17 @@ lazy val scalaTestSettings = Seq(

// -- Rocket Chip --

lazy val hardfloat = freshProject("hardfloat", file("generators/hardfloat/hardfloat"))
.settings(chiselSettings)
.settings(commonSettings)
.dependsOn(midas_target_utils)
.settings(scalaTestSettings)
lazy val hardfloat = {
val useChisel7 = sys.env.contains("USE_CHISEL7")
var hf = freshProject("hardfloat", file("generators/hardfloat/hardfloat"))
.settings(chiselSettings)
.settings(commonSettings)
.settings(scalaTestSettings)
if (!useChisel7) {
hf = hf.dependsOn(midas_target_utils)
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oh... how does this work? regardless of useChisel7 or not, wouldn't hf require midas as a dependency?

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I think this was our hacky way to make everything depend on midas-target-utils in the pre-chisel7 flow

}
hf
}

lazy val rocketMacros = (project in rocketChipDir / "macros")
.settings(commonSettings)
Expand Down Expand Up @@ -154,24 +166,55 @@ lazy val testchipip = withInitCheck((project in file("generators/testchipip")),
.settings(commonSettings)

lazy val chipyard = {
val useChisel7 = sys.env.contains("USE_CHISEL7")
// Base chipyard project with always-on dependencies
// Use explicit Project(...) so the project id remains 'chipyard'
var cy = Project(id = "chipyard", base = file("generators/chipyard"))
.dependsOn(
val baseProjects: Seq[ProjectReference] =
Seq(
testchipip, rocketchip, boom, rocketchip_blocks, rocketchip_inclusive_cache,
dsptools, rocket_dsp_utils,
icenet, tracegen,
constellation, barf, shuttle, rerocc,
firrtl2_bridge
)
).map(sbt.Project.projectToRef) ++
(if (useChisel7) Seq() else Seq(sbt.Project.projectToRef(firrtl2_bridge))) ++
(if (useChisel7) Seq() else Seq(sbt.Project.projectToRef(dsptools), sbt.Project.projectToRef(rocket_dsp_utils)))

val baseDeps: Seq[sbt.ClasspathDep[sbt.ProjectReference]] =
baseProjects.map(pr => sbt.ClasspathDependency(pr, None))

// Optional settings to exclude specific sources under Chisel 7
val dspExcludeSettings: Seq[Def.Setting[_]] = if (useChisel7) Seq(
Compile / unmanagedSources := {
val files = (Compile / unmanagedSources).value
val root = (ThisBuild / baseDirectory).value
val excludeList = Seq(
// Directories or files relative to repo root
"generators/chipyard/src/main/scala/example/dsptools",
"generators/chipyard/src/main/scala/config/MMIOAcceleratorConfigs.scala",
"generators/chipyard/src/main/scala/config/TutorialConfigs.scala",
"generators/chipyard/src/main/scala/upf"
).map(p => (root / p).getCanonicalFile)
val (excludeDirs, excludeFiles) = excludeList.partition(_.isDirectory)
files.filterNot { f =>
val cf = f.getCanonicalFile
excludeFiles.contains(cf) || excludeDirs.exists(d => cf.toPath.startsWith(d.toPath))
}
}
) else Seq.empty

var cy = Project(id = "chipyard", base = file("generators/chipyard"))
.dependsOn(baseDeps: _*)
.settings(libraryDependencies ++= rocketLibDeps.value)
.settings(
libraryDependencies ++= Seq(
"org.reflections" % "reflections" % "0.10.2"
)
)
.settings(commonSettings)
.settings(Compile / unmanagedSourceDirectories += file("tools/stage/src/main/scala"))
.settings(Compile / unmanagedSourceDirectories += {
if (useChisel7) file("tools/stage-chisel7/src/main/scala")
else file("tools/stage/src/main/scala")
})
.settings(dspExcludeSettings: _*)

// Optional modules discovered via initialized submodules (no env or manifest)
val optionalModules: Seq[(String, ProjectReference)] = Seq(
Expand Down
53 changes: 51 additions & 2 deletions common.mk
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Original file line number Diff line number Diff line change
Expand Up @@ -16,6 +16,21 @@ define require_cmd
|| { echo "Error: $(1) not found in PATH. Set up your tool environment before building this target." >&2; exit 1; }
endef

# Require minimum firtool version when building with Chisel 7
define require_firtool_version
@if [ -n "$(USE_CHISEL7)" ]; then \
vline=`$(FIRTOOL_BIN) --version 2>/dev/null | grep -E 'CIRCT firtool-[0-9]+\.[0-9]+\.[0-9]+' | head -1`; \
vstr=$${vline##*firtool-}; \
if [ -z "$$vstr" ]; then \
echo "Error: Unable to parse firtool version. Ensure '$(FIRTOOL_BIN) --version' prints 'CIRCT firtool-X.Y.Z'." >&2; exit 1; \
fi; \
maj=$${vstr%%.*}; rest=$${vstr#*.}; min=$${rest%%.*}; pat=$${rest#*.}; \
if [ "$$maj" -lt 1 ] || { [ "$$maj" -eq 1 ] && [ "$$min" -lt 129 ]; }; then \
echo "Error: USE_CHISEL7 requires firtool >= 1.129.0, found $$vstr. Please update CIRCT firtool." >&2; exit 1; \
fi; \
fi
endef

#########################################################################################
# specify user-interface variables
#########################################################################################
Expand Down Expand Up @@ -68,7 +83,9 @@ HELP_COMMANDS += \
" run-tests = run all assembly and benchmark tests" \
" launch-sbt = start sbt terminal" \
" find-configs = list Chipyard Config classes (eligible CONFIG=)" \
" find-config-fragments = list all config. fragments"
" find-config-fragments = list all config. fragments" \
" run-firtool = run CIRCT firtool to emit Verilog/JSON/mem conf" \
" run-uniquify = run uniquify-module-names on current elaboration outputs"

#########################################################################################
# include additional subproject make fragments
Expand Down Expand Up @@ -159,6 +176,9 @@ export mfc_extra_anno_contents
export sfc_extra_low_transforms_anno_contents
$(FINAL_ANNO_FILE) $(MFC_EXTRA_ANNO_FILE) &: $(ANNO_FILE)
echo "$$mfc_extra_anno_contents" > $(MFC_EXTRA_ANNO_FILE)
ifdef USE_CHISEL7
jq '. + [{"class":"firrtl.transforms.BlackBoxTargetDirAnno","targetDir":"$(GEN_COLLATERAL_DIR)/blackboxes"}]' $(MFC_EXTRA_ANNO_FILE) > $(MFC_EXTRA_ANNO_FILE).tmp && mv $(MFC_EXTRA_ANNO_FILE).tmp $(MFC_EXTRA_ANNO_FILE)
endif
jq -s '[.[][]]' $(ANNO_FILE) $(MFC_EXTRA_ANNO_FILE) > $(FINAL_ANNO_FILE)

.PHONY: firrtl
Expand All @@ -179,6 +199,12 @@ SFC_MFC_TARGETS = \

MFC_BASE_LOWERING_OPTIONS ?= emittedLineLength=2048,noAlwaysComb,disallowLocalVariables,verifLabels,disallowPortDeclSharing,locationInfoStyle=wrapInAtSquareBracket

# Extra firtool flags are only applied when building with Chisel 7
FIRTOOL_EXTRA_FLAGS ?=
ifdef USE_CHISEL7
FIRTOOL_EXTRA_FLAGS += --verification-flavor=if-else-fatal --disable-layers=Verification.Assume,Verification.Cover
endif

# DOC include start: FirrtlCompiler
$(MFC_LOWERING_OPTIONS):
mkdir -p $(dir $@)
Expand All @@ -190,6 +216,7 @@ endif

$(SFC_MFC_TARGETS) &: $(FIRRTL_FILE) $(FINAL_ANNO_FILE) $(MFC_LOWERING_OPTIONS)
$(call require_cmd,$(FIRTOOL_BIN))
$(require_firtool_version)
rm -rf $(GEN_COLLATERAL_DIR)
(set -o pipefail && $(FIRTOOL_BIN) \
--format=fir \
Expand All @@ -204,12 +231,34 @@ $(SFC_MFC_TARGETS) &: $(FIRRTL_FILE) $(FINAL_ANNO_FILE) $(MFC_LOWERING_OPTIONS)
--repl-seq-mem-file=$(MFC_SMEMS_CONF) \
--annotation-file=$(FINAL_ANNO_FILE) \
--split-verilog \
$(FIRTOOL_EXTRA_FLAGS) \
-o $(GEN_COLLATERAL_DIR) \
$(FIRRTL_FILE) |& tee $(FIRTOOL_LOG_FILE))
$(SED) $(SED_INPLACE) 's/.*/& /' $(MFC_SMEMS_CONF) # need trailing space for SFC macrocompiler
touch $(MFC_BB_MODS_FILELIST) # if there are no BB's then the file might not be generated, instead always generate it
ifdef USE_CHISEL7
# Construct blackbox file list from files emitted into gen-collateral/blackboxes
@if [ -d "$(GEN_COLLATERAL_DIR)/blackboxes" ]; then \
find "$(GEN_COLLATERAL_DIR)/blackboxes" -type f \( -name '*.v' -o -name '*.sv' -o -name '*.cc' \) | \
sed -e 's;^$(GEN_COLLATERAL_DIR)/;;' > "$(MFC_BB_MODS_FILELIST)"; \
else \
: > "$(MFC_BB_MODS_FILELIST)"; \
fi
else
# If there are no BB's then the file might not be generated; ensure it exists
touch $(MFC_BB_MODS_FILELIST)
endif
# DOC include end: FirrtlCompiler

.PHONY: run-firtool
run-firtool: $(SFC_MFC_TARGETS)
@echo "[run-firtool] Generated: $(SFC_MFC_TARGETS)"

# Convenience alias to re-run the uniquify step (module/filelist splitting)
.PHONY: run-uniquify
run-uniquify: $(TOP_MODS_FILELIST) $(MODEL_MODS_FILELIST) $(ALL_MODS_FILELIST) $(BB_MODS_FILELIST) $(MFC_MODEL_HRCHY_JSON_UNIQUIFIED)
@echo "[run-uniquify] Updated filelists under $(GEN_COLLATERAL_DIR)"


$(TOP_MODS_FILELIST) $(MODEL_MODS_FILELIST) $(ALL_MODS_FILELIST) $(BB_MODS_FILELIST) $(MFC_MODEL_HRCHY_JSON_UNIQUIFIED) &: $(MFC_MODEL_HRCHY_JSON) $(MFC_TOP_HRCHY_JSON) $(MFC_FILELIST) $(MFC_BB_MODS_FILELIST)
$(base_dir)/scripts/uniquify-module-names.py \
--model-hier-json $(MFC_MODEL_HRCHY_JSON) \
Expand Down
2 changes: 1 addition & 1 deletion generators/rocket-chip
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Submodule rocket-chip updated 10 files
+10 −10 .github/workflows/mill-ci.yml
+2 −2 src/main/scala/amba/ahb/Nodes.scala
+1 −1 src/main/scala/amba/apb/Nodes.scala
+1 −1 src/main/scala/amba/axi4/Nodes.scala
+2 −2 src/main/scala/devices/debug/Debug.scala
+2 −2 src/main/scala/rocket/CSR.scala
+1 −1 src/main/scala/rocket/TLB.scala
+1 −1 src/main/scala/tilelink/Nodes.scala
+1 −1 src/main/scala/trace/TraceSinkArbiter.scala
+1 −1 src/main/scala/trace/TraceSinkMonitor.scala
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