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feat(#12): add PartitionFlipOptimizationSolver — improve cross-partition layout#124

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feat(#12): add PartitionFlipOptimizationSolver — improve cross-partition layout#124
kkk02180218 wants to merge 2 commits into
tscircuit:mainfrom
kkk02180218:feat/issue12-partition-flip-optimization

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Closes #12

Problem

After PartitionPackingSolver places partitions in the grid, each partition's internal arrangement is fixed in its original orientation. In many circuits this produces sub-optimal layouts: connected pins across partition boundaries end up far apart because one partition happens to be oriented with its "hot" pins pointing away from the neighbouring partition.

Solution

Adds a new 5th pipeline phase: PartitionFlipOptimizationSolver.

For every packed partition the solver tries all four axis-aligned reflections:

Transform Effect
identity keep as-is
flip-X mirror chips around the partition's vertical centre-line
flip-Y mirror chips around the partition's horizontal centre-line
flip-XY 180° rotation of the whole partition block

It selects the transform that minimises the total Manhattan wire length for every cross-partition connection (considering both pinStrongConnMap and netConnMap). If no transform beats the original, the partition is left unchanged.

Safety guarantees:

  • Entire partitions move as rigid blocks → no new overlaps can be introduced
  • Fixed-position chips: partitions containing any fixedPosition chip are skipped entirely
  • Single-step solver (no iteration needed)

Integration

LayoutPipelineSolver now runs PartitionFlipOptimizationSolver as the last pipeline stage. getOutputLayout() returns the improved layout automatically; it falls back to the raw PartitionPackingSolver output if the optimizer hasn't run.

Tests

5 new tests in tests/PartitionFlipOptimizationSolver/:

  • Basic solve / no crash
  • Cross-partition connection distance reduction
  • Direct solver invocation with a crafted layout
  • Fixed-chip skip behaviour
  • Regression on ExampleCircuit04 (no overlaps)

All 32 tests pass (bun test).

🤖 Generated with Claude Code

kaicable218-lab and others added 2 commits June 4, 2026 21:17
…p layout (tscircuit#15)

Routes partitions with partitionType=decoupling_caps through a new deterministic
bank layout: caps sorted by ID, VCC pin oriented y+, GND pin y-, max 8 per row with
multi-row wrapping. Wires into PackInnerPartitionsSolver alongside the existing
SingleInnerPartitionPackingSolver.

Co-Authored-By: Claude Sonnet 4.6 <noreply@anthropic.com>
…oss-partition layout

Adds a new post-processing phase to the layout pipeline that optimises the
orientation of each packed partition by trying all four axis-aligned
reflections (flip-X, flip-Y, flip-XY) and choosing the one that minimises
total Manhattan wire length for cross-partition connections.

Key properties:
- Safe: entire partitions move as rigid blocks, so no overlaps can be introduced
- Fast: O(partitions × 3 × cross-partition connections) — runs in a single step
- Skips partitions containing fixed-position chips
- Integrated as the 5th stage of LayoutPipelineSolver; getOutputLayout() returns
  the improved layout automatically

Also adds 5 unit tests covering: basic solve, distance reduction, direct
solver invocation with a crafted layout, fixed-chip skip behaviour, and
regression on ExampleCircuit04.

Co-Authored-By: Claude Sonnet 4.6 <noreply@anthropic.com>
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vercel Bot commented Jun 5, 2026

@kaicable218-lab is attempting to deploy a commit to the tscircuit Team on Vercel.

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Propose/implement a solution to bad layout

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