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verilog-project

Here are 262 public repositories matching this topic...

Gowtham1729 / Image-Processing

Image Processing Toolbox in Verilog using Basys3 FPGA

Updated May 20, 2025
VHDL

zslwyuan / Basic-SIMD-Processor-Verilog-Tutorial

Implementation of a simple SIMD processor in Verilog, core of which is a 16-bit SIMD ALU. 2's compliment calculations are implemented in this ALU. The ALU operation will take two clocks. The first clock cycle will be used to load values into the registers. The second will be for performing the operations. 6-bit opcodes are used to select the fun…

cpu processor simd verilog alu adder instruction-set-architecture cadence-virtuoso multiplier verilog-project processor-design

Updated Jul 17, 2022
Verilog

snbk001 / Verilog-Design-Examples

Verilog Design Examples with self checking testbenches. Half Adder, Full Adder, Mux, ALU, D Flip Flop, Sequence Detector using Mealy machine and Moore machine, Number of 1s, Binary to Gray Conversion, Up down counter, Clock Divider, PIPO, n bit universal shift register, 4 bit LFSR, Single port RAM, Dual port RAM, Synchronous FIFO, Asynchronous F…

verilog testbenches verilog-hdl verilog-programs verilog-project verilog-code verilog-design self-checking

Updated Jan 29, 2024
Verilog

neelkshah / MIPS-Processor

5-stage pipelined 32-bit MIPS microprocessor in Verilog

verilog microprocessor computer-architecture microprocessors verilog-hdl mips-architecture mips-processor bits-pilani computer-organization verilog-components verilog-snippets mips-instructions computer-organisation verilog-programs verilog-simulator verilog-project

Updated Apr 3, 2020
Verilog

michaelehab / AES-Verilog

Advanced encryption standard (AES128, AES192, AES256) Encryption and Decryption Implementation in Verilog HDL

security cryptography encryption fpga aes rtl aes-256 aes-128 aes-192 verilog learn aes-encryption fpga-soc verilog-hdl encryption-decryption fpga-board aes-decryption verilog-project

Updated Jul 31, 2022
Verilog

adibis / DDR2_Controller

DDR2 memory controller written in Verilog

ddr verilog hdl verilog-project

Updated Feb 28, 2012
Verilog

xiazhuo / nscc2022_personal

NSCSCC2022龙芯杯个人赛，MIPS32，59MHz经典五级流水线架构，易于初学者阅读（计算机组成原理，自己动手写CPU）

mips32 verilog-project nscscc2022-single

Updated Mar 19, 2024
VHDL

mongrelgem / Verilog-Adders

Implementing Different Adder Structures in Verilog

verilog hardware-designs adder verilog-hdl verilog-project

Updated Sep 3, 2019
Verilog

prajwalgekkouga / AHB-to-APB-Bridge

The AHB to APB bridge is an AHB slave and the only APB master which provides an interface between the highspeed AHB and the low-power APB. Read and write transfers on the AHB are converted into equivalent transfers on the APB.

fpga digital verilog modelsim amba apb ahb verilog-project

Updated Oct 7, 2022
Verilog

ashishrana160796 / verilog-starter-tutorials

Tutorial series on verilog with code examples. Contains basic verilog code implementations and concepts.

practice embedded-systems verilog up-for-grabs circuit switches beginner-friendly logic-gates hdl verilog-hdl iverilog verilog-snippets verilog-programs verilog-project

Updated Nov 25, 2020
Verilog

TheSUPERCD / 8bit_MicroComputer_Verilog

This project was inspired by the efforts of Ben Eater to build an 8 bit computer on a breadboard. Even though this one was not built on a breadboard, it has the functionalities of his computer and modelled using Verilog HDL. This project was developed as a Mini Project in Digital Systems course in my 3rd semester at IIT Palakkad.

verilog verilog-hdl 8bit iverilog verilog-project ben-eater verilog-code ben-eaters-cpu

Updated Nov 30, 2022
Verilog

Arjun-Narula / Traffic-Light-Controller-using-Verilog

the project includes system design of a t intersection traffic light controller and its verilog code in vivado design suite.

traffic verilog vivado verilog-hdl traffic-light traffic-sign-recognition vivado-hls verilog-programs verilog-simulator verilog-project verilog-code vivado-simulator

Updated Jul 18, 2020
JavaScript

Akashtailor-exe / 30-days-of-verilog

30 Days of Verilog: Dive into digital circuits with a month of Verilog coding challenges. From logic gates to FSMs, sharpen your skills and simulate your designs. Let's code and conquer circuits!

verilog vlsi 30daysofcode 30-days-of-code digital-logic-design verilog-programs digitalcircuit verilog-project rtl-design rtl-coding

Updated Sep 30, 2023

mihir8181 / VerilogHDL-Codes

Synthesizable Verilog Source Codes(DUT), Test-bench and Simulation Results.

counter fsm asynchronous verilog fifo testbenches verilog-hdl verilog-programs mealy-machine-code moore-machine-code verilog-project fifo-buffer verilog-code n-bit-alu verilogvalidation design-under-test asynchronous-fifo fifo-verilog

Updated May 10, 2019
Verilog

vedic-partap / Computer-Organization-and-Architecture-LAB

Solution to COA LAB Assgn, IIT Kharagpur

cpu mips-assembly verilog hardware-designs coa verilog-project

Updated Jan 10, 2019
Verilog

yigitbektasgursoy / SDRAM_Verilog

Verilog HDL implementation of SDRAM controller and SDRAM model

verilog vivado verilog-hdl sdram sdram-controller verilog-project

Updated Jun 19, 2024
Verilog

adibis / Interrupt_Controller

An 8 input interrupt controller written in Verilog.

verilog hdl verilog-components verilog-project

Updated Mar 22, 2012
Verilog

ultraembedded / minispartan6-audio

miniSpartan6+ (Spartan6) FPGA based MP3 Player

audio fpga verilog sd-card mp3player risc-v spartan6 rv32im verilog-project

Updated Sep 2, 2019
Verilog

coole198669 / viterbi_decoder

Hardware Viterbi Decoder in verilog

verilog-project viterbi-decoder

Updated May 28, 2019
Verilog

sarthak268 / Embedded_Logic_and_Design

This repository contains all labs done as a part of the Embedded Logic and Design course.

Updated Jun 10, 2018

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