Update README.md

labs/project/README.md

@@ -25,10 +25,12 @@ The aim of the project is to cooperate in small teams, to study the subject, to
 
 * **Never, ever** use `rising_edge` or `falling_edge` to test edges of non-clock signals under any circumstances!
 
-* In a synchronous process, the first thing to do is test the clock edge, then synchronous reset. The only exception is asynchronous operations.
-
 * Use hierarchical design, ie. instances, top-level, several files, etc.
 
+* Use synchronous entities with clk.
+
+* In a synchronous process, the first thing to do is test the clock edge, then synchronous reset. The only exception is asynchronous operations.
+
 * Use only input `in` or output `out` ports and not ~~inout~~.
 
 * Use `wait` statements [only in simulations](https://www.vhdl-online.de/courses/system_design/vhdl_language_and_syntax/sequential_statements/wait_statement).