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AP Float Tutorial #3

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tiwaria1 wants to merge 7 commits into master from ap_float_tutorial

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tiwaria1 commented Oct 14, 2021

Internal review of ap_float tutorial. This is a port of the 3 HLS ap_float tutorials.

Testing:
[DONE] Linux Local compile
[TODO] Linux Local compile with CMAKE
[TODO] Linux Regtest
[TODO] Windows Local compile with CMAKE
[TODO] Windows Regtest

tiwaria1 added 4 commits

October 14, 2021 09:07


          first draft

6c23901


          add -Wall, do not pass actypes flag to report linking stage

dfd8431


          specify sycl:: for isnan call, clang format again

fbbe685

Without this namespace clarification, the tutorial will not compile on Windows


          test fix for sln file

03e6951

whitepau suggested changes

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whitepau left a comment

I really like your tutorials, Abhishek. This one is pretty long, but overall I think it is composed of many bite-sized pieces. Perhaps one could argue for parcelling them out into smaller tutorials, but I know that having many tutorials can be overwhelming for users.

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DirectProgramming/DPC++FPGA/Tutorials/Features/ac_types/ap_float/README.md Outdated

+              ```cpp
+              ihc::ap_float<EW, MW> a;
+              ```
+              Here EW specifies the exponent width and MW specifies the mantissa width of the number. Optionally, another template parameter can be specified to set the rounding mode. For more details please refer to the section titled `Variable-Precision Integer and Floating-Point Support` in the Intel® oneAPI DPC++ FPGA Optimization Guide.

whitepau Oct 15, 2021

I think that we should explicitly describe floating points, either here or in the other documentation, and include a picture like this:

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DirectProgramming/DPC++FPGA/Tutorials/Features/ac_types/ap_float/src/ap_float.cpp

+                // We set the rounding mode to RZERO (truncate to zero) because this allows us
+                // to generate compile-time ap_float constants from double type literals shown
+                // below, which eliminates the area usage for initialization.
+                using APDoubleTypeC = ihc::ap_float<11, 44, kRoundingModeRZERO>;

whitepau Oct 18, 2021

I tried to test this but I couldn't get it to compile in HUB with these directions. My concern is that I believe we should show that it's possible to get identical performance between a native float/double and a similarly configured ap_float type. This was an issue in HLS.

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whitepau reviewed

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whitepau left a comment

Part 2

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DirectProgramming/DPC++FPGA/Tutorials/Features/ac_types/ap_float/README.md Outdated


		In C++ applications, the basic binary operations have little expressiveness. On the contrary, FPGAs implement these operations using configurable logic, so you can improve your design's performance by fine-tuning the floating-point operations since they are usually area and latency intensive.

		The kernel `SpecializedQuadraticEqnSolverKernel` demonstrates how to use the explicit versions of `ap_float` binary operators to perform floating-point arithmetic operations based on your need.

whitepau Oct 18, 2021

T

Suggested change

      
            The kernel `SpecializedQuadraticEqnSolverKernel` demonstrates how to use the explicit versions of `ap_float` binary operators to perform floating-point arithmetic operations based on your need.
          
            The kernel code in the function `TestSpecializedQuadraticEqnSolver()` demonstrates how to use the explicit versions of `ap_float` binary operators to perform floating-point arithmetic operations based on your need.

I won't fix these anymore, but please update them.

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DirectProgramming/DPC++FPGA/Tutorials/Features/ac_types/ap_float/README.md


		You should observe an area reduction of up to 30% in resource utilization of the binary operations.

		TODO: Is simulation supported for customers yet?

whitepau Oct 18, 2021

good question...

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+              Expand the lines with the kernel names by clicking on them and expand the sub hierarchies to observe how the `add, mult` and `div`
+              operations use lesser resources for the `ApproximateSineWithAPFloat` kernel.
+              You should observe an area reduction of up to 30% in resource utilization of the binary operations.

whitepau Oct 18, 2021

Suggested change

      
            You should observe an area reduction of up to 30% in resource utilization of the binary operations.
          
            You should observe an area reduction in resource utilization of up to 30% for the binary operations.

perhaps include a before/after screenshot? I know my first instinct would be to compare the overall area in the summary report.

DirectProgramming/DPC++FPGA/Tutorials/Features/ac_types/ap_float/README.md

+. Kernel: `ConversionKernelC`
+                This kernel shows how to use the `convert_to` function and modify the rounding mode for a specific operation.
+                In the graph for the cluster under `Kernel_C`, you will find that it contains two "cast" nodes, corresponding to the conversions:

whitepau Oct 18, 2021

does it make sense to include screenshots? probably not since we change the report graphics so much.

whitepau reviewed

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DirectProgramming/DPC++FPGA/Tutorials/Features/ac_types/ap_float/README.md Outdated

+              #include <sycl/ext/intel/ac_types/ap_float_math.hpp>
+              ```
+              Additionally, you must use the flag `-qactypes` in order to ensure that the headers are correctly included and that the compiler links against the necessary libraries for emulation support.

whitepau Oct 20, 2021

please tell the user where the -qactypes or /Qactypes flag appears.

Owner Author

tiwaria1 Nov 1, 2021

Added a note, however I might have the -fintelfpga flag absorb -qactypes before this tutorial is released.

tiwaria1 added 3 commits

November 1, 2021 14:21


          address review comments

e088883


          minor comment

2e20071


          update samples.json

a373e47

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