[AscendNPU-IR][A5] Added A5 support for FlipOp#911
[AscendNPU-IR][A5] Added A5 support for FlipOp#911Ismayil06 wants to merge 1 commit intotile-ai:npuir-devfrom
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Code Review
This pull request updates the VflipCodegen implementation in codegen_npuir_dev.cc to utilize mlir::hfusion::FlipOp and ReshapeCastAndInsertSlice, and introduces a new test file to verify the functionality. A redundant double assignment was found in the VflipCodegen function that should be simplified.
| builder.create<mlir::hivm::VFlipOp>(builder.getUnknownLoc(), TypeRange{}, src, | ||
| dst, npuirop.axis); | ||
| Value src = GenExtractSliceFromRegion(npuirop.src, npuirop.src_range); | ||
| Value dst = dst = GetVarValue(npuirop.dst); |
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There is a typo in the assignment: Value dst = dst = .... This redundant double assignment is likely a copy-paste error and should be corrected to a single assignment to avoid potential issues with using an uninitialized variable.
Value dst = GetVarValue(npuirop.dst);
| a = T.alloc_shared((M, N), dtype) | ||
| b = T.alloc_shared((M, N), dtype) | ||
| T.copy(A, a) | ||
| T.npuir_flip(a, b, axis) |
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This test case do not trigger GenExtractSliceFromRegion, if don't support, please use GetVarValue
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also, Please use flip
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| auto loc = builder.getUnknownLoc(); | ||
| auto srcTy = src.getType().cast<RankedTensorType>(); | ||
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| auto flipOp = builder.create<mlir::hfusion::FlipOp>(loc, srcTy, src, static_cast<uint64_t>(npuirop.axis)); |
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If a negative axis is passed upstream (e.g., axis=-1 in Python), the implicit int64_t → u_int64_t conversion would produce a huge unsigned value. Add negative axis legalization in the NpuirFlip constructor (converting negative to positive), or add an ICHECK(npuirop.axis >= 0) assertion in VflipCodegen .
| B_VEC = T.alloc_shared((M, N), dtype) | ||
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| T.copy(A, A_VEC) | ||
| T.npuir_flip(A_VEC, B_VEC, axis) |
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[AscendNPU-IR][A5] Added A5 support for FlipOp
- Changed hivm::VFlipOp to hfusion::FlipOp
- Added pytest for FlipOp