Process Element

Architecture

Pipeline timing diagram

FSM States

• Idle, accumulator reset (IDL)
• Init, clear registers (INT)
• Register A preload (RPA)
• Register B preload (RPB)
• Halt, output FIFO full; wait for spad to be ready (HLT)
• Accumulate input psum (ACCU)
• Bit-serial multiply and accumulate from register A (MACA)
• Bit-serial multiply and accumulate from register B (MACB)

Multiply and add circuitry