riscv64: support genode boot

Cargo.toml

@@ -48,6 +48,7 @@ acpi = "=5.2.0"
 ############# general ##############
 iommu = [] # supported by: aarch64
 pci = [] # supported by: aarch64, loongarch64
+print_timestamp = [] # print timestamp when logging
 
 ############# aarch64 ##############
 # irqchip driver

platform/riscv64/hifive-premier-p550/board.rs

@@ -19,6 +19,8 @@ use crate::{arch::zone::HvArchZoneConfig, config::*};
 pub const BOARD_NAME: &str = "hifive-premier-p550";
 
 pub const BOARD_NCPUS: usize = 4;
+pub const TIMEBASE_FREQ: u64 = 0xf4240; // 1MHz
+
 pub const PLIC_BASE: usize = 0xc000000;
 pub const BOARD_PLIC_INTERRUPTS_NUM: usize = 1023; // except irq 0
 pub const SIFIVE_CCACHE_BASE: usize = 0x2010000; // SiFive composable cache controller
@@ -140,16 +142,28 @@ pub const ROOT_ZONE_MEMORY_REGIONS: [HvConfigMemoryRegion; 7] = [
 
 // Note: all here's irqs are hardware irqs,
 //  only these irq can be transferred to the physical PLIC.
-pub const HW_IRQS: [u32; 3] = [
+pub const HW_IRQS: [u32; 21] = [
+    0x1, 0x2, 0x3, 0x4, // cache controller
     0x4f, // emmc
     0x51, // sd-card
-    0x64  // uart0
+    0x64,  // uart0
+    0x164, 0x168, 0x165, 0x166, // iommu
+    0x183, // npu
+    0x75, 0x77, 0x79, 0x7b, 0x7d, 0x7f, 0x81, 0x83, // mailbox
+    0x123, // i2c
+    // 0x01, 0x03, 0x04, 0x02, // cache controller
 ];
 
 // irqs belong to the root zone.
-pub const ROOT_ZONE_IRQS: [u32; 2] = [
+pub const ROOT_ZONE_IRQS: [u32; 20] = [
+    0x1, 0x2, 0x3, 0x4, // cache controller
     0x51, // sd-card
-    0x64  // uart0
+    0x64,  // uart0
+    0x164, 0x168, 0x165, 0x166, // iommu
+    0x183, // npu
+    0x75, 0x77, 0x79, 0x7b, 0x7d, 0x7f, 0x81, 0x83, // mailbox
+    0x123, // i2c
+    // 0x01, 0x03, 0x04, 0x02, // cache controller
 ];
 
 pub const ROOT_ARCH_ZONE_CONFIG: HvArchZoneConfig = HvArchZoneConfig {