Merge new features to main for hvisor-v0.2 release

.gitignore

@@ -30,7 +30,7 @@ flash.img*
 compile.sh
 src/platform/__board.rs
 .config
+.cursorrules
 .vscode/extensions.json
-
 # systemtest
 rootfs1.zip*

.vscode/settings-example.json

@@ -14,6 +14,6 @@
 	// "rust-analyzer.cargo.target": "riscv64gc-unknown-none-elf",
 	// "rust-analyzer.cargo.target": "loongarch64-unknown-none",
 	"rust-analyzer.cargo.features": [
-	    "gicv3 pl011 iommu pci pt_layout_qemu"
+	    "gicv3 pl011 iommu pci"
 	]
 }

Cargo.toml

@@ -7,7 +7,7 @@ edition = "2021"
 
 [dependencies]
 log = "0.4"
-spin = "0.9"
+spin = "0.10.0"
 bitflags = "2.1"
 bit_field = "0.10"
 numeric-enum-macro = "0.2"
@@ -20,6 +20,7 @@ qemu-exit = "3.0.2"
 cortex-a = "8.1.1"
 cfg-if = "1.0"
 bitvec = { version="1.0.1", default-features = false, features = ["atomic", "alloc"] }
+heapless = { version = "0.8.0 "}
 
 [dependencies.fdt-rs]
 version = "0.4.5"
@@ -31,15 +32,15 @@ psci = { version = "0.1.0", default-features = false, features = ["smc"]}
 
 [target.'cfg(target_arch = "riscv64")'.dependencies]
 sbi-rt = { version = "0.0.3", features = ["legacy"] }
-sbi-spec = "0.0.8"
+sbi-spec = { version = "0.0.8", features = ["legacy"]}
 riscv = "0.13.0"
 riscv_h = { package = "riscv", git = "https://github.com/rcore-os/riscv", features = ["inline-asm"] }
 riscv-decode = "0.2.1"
 riscv-peripheral = "0.2.1"
 riscv-pac = "0.2.0"
 
 [target.'cfg(target_arch = "loongarch64")'.dependencies]
-loongArch64 = "0.2.4"
+loongArch64 = "0.2.5"
 
 [target.'cfg(target_arch = "x86_64")'.dependencies]
 x86 = "0.52.0"
@@ -62,20 +63,8 @@ pl011 = []
 xuartps = []
 imx_uart = []
 uart_16550 = []
-
-# pagetable layout
-pt_layout_qemu = []
-pt_layout_rk3568 = []
-pt_layout_rk3588 = []
-pt_layout_zcu102 = []
-
-# cpu
-mpidr_rockchip = []
-
-# uart infos
-uart_base_rk3568 = []
-uart_base_rk3588 = []
-uart_base_ok6254 = []
+sifive_ccache = []
+eic7700_sysreg = []
 
 ############## riscv64 #############
 # irqchip driver
@@ -84,13 +73,20 @@ aia = []
 aclint = []
 # extensions
 sstc = []
+# platform specific
+eic770x_soc = []
+
 ########### loongarch64 ############
 # irqchip driver
 loongson_7a2000 = []
 # uart driver
 loongson_uart = []
+# cpu (not used for now)
+loongson_3a5000 = []
+loongson_3a6000 = []
 
 
 [profile.dev]
 # panic = "abort" # avoid cargo test failure, this is a bug of cargo
 debug = 2
+opt-level = 0 

README-zh.md

@@ -62,6 +62,8 @@ hvisor 是一个用 Rust 实现的 Type-1 裸机虚拟机监控器，采用分
 ### riscv64
 
 - [x] QEMU virt riscv64
+- [x] Milk-V Megrez
+- [x] Sifive Hifive Premier P550
 - [ ] FPGA 香山（昆明湖）on S2C Prodigy S7-19PS-2
 - [ ] FPGA  RocketChip on Xilinx Ultrascale+ MPSoC ZCU102
 

README.md

@@ -62,13 +62,15 @@ hvisor is a Type-1 bare-metal virtual machine monitor implemented in Rust, featu
 ### riscv64
 
 - [x] QEMU virt riscv64
+- [x] Milk-V Megrez
+- [x] Sifive Hifive Premier P550
 - [ ] FPGA XiangShan(KunMingHu) on S2C Prodigy S7-19PS-2
 - [ ] FPGA RocketChip on Xilinx Ultrascale+ MPSoC ZCU102
 
 ### loongarch64
 
 - [x] Loongson 3A5000 (7A2000 bridge chip)
-- [ ] Loongson 3A6000 (7A2000 bridge chip)
+- [x] Loongson 3A6000 (7A2000 bridge chip)
 
 ## Getting Started
 

platform/aarch64/imx8mp/board.rs

@@ -13,11 +13,33 @@
 //
 // Authors:
 //
-use crate::{arch::zone::HvArchZoneConfig, config::*};
+use crate::{
+    arch::{mmu::MemoryType, zone::HvArchZoneConfig},
+    config::*,
+};
 
 pub const BOARD_NAME: &str = "imx8mp";
 
 pub const BOARD_NCPUS: usize = 4;
+pub const BOARD_UART_BASE: u64 = 0x30890000;
+
+#[rustfmt::skip]
+pub static BOARD_MPIDR_MAPPINGS: [u64; BOARD_NCPUS] = [
+    0x0,   // cpu0
+    0x1,   // cpu1
+    0x2,   // cpu2
+    0x3,   // cpu3
+];
+
+/// The physical memory layout of the board.
+/// Each address should align to 2M (0x200000).
+/// Addresses must be in ascending order.
+#[rustfmt::skip]
+pub const BOARD_PHYSMEM_LIST: &[(u64, u64, MemoryType)] = &[
+ // (       start,           end,                type)
+    (         0x0,    0x40000000,  MemoryType::Device),
+    (  0x40000000,   0x100000000,  MemoryType::Normal),
+];
 
 pub const ROOT_ZONE_DTB_ADDR: u64 = 0xa0000000;
 pub const ROOT_ZONE_KERNEL_ADDR: u64 = 0xa0400000;
@@ -103,6 +125,7 @@ pub const ROOT_ARCH_ZONE_CONFIG: HvArchZoneConfig = HvArchZoneConfig {
     gicv_size: 0,
     gits_base: 0,
     gits_size: 0,
+    is_aarch32: 0,
 };
 
 pub const ROOT_ZONE_IVC_CONFIG: [HvIvcConfig; 0] = [];

platform/aarch64/ok6254-c/board.rs

@@ -14,10 +14,33 @@
 // Authors:
 //
 
-use crate::{arch::zone::HvArchZoneConfig, config::*};
+use crate::{
+    arch::{mmu::MemoryType, zone::HvArchZoneConfig},
+    config::*,
+};
 
 pub const BOARD_NAME: &str = "ok6254";
 pub const BOARD_NCPUS: usize = 4;
+pub const BOARD_UART_BASE: u64 = 0x2800000;
+
+
+#[rustfmt::skip]
+pub static BOARD_MPIDR_MAPPINGS: [u64; BOARD_NCPUS] = [
+    0x0,   // cpu0
+    0x1,   // cpu1
+    0x2,   // cpu2
+    0x3,   // cpu3
+];
+
+/// The physical memory layout of the board.
+/// Each address should align to 2M (0x200000).
+/// Addresses must be in ascending order.
+#[rustfmt::skip]
+pub const BOARD_PHYSMEM_LIST: &[(u64, u64, MemoryType)] = &[
+ // (       start,           end,                type)
+    (         0x0,    0x80000000,  MemoryType::Device),
+    (  0x80000000,   0x100000000,  MemoryType::Normal),
+];
 
 pub const ROOT_ZONE_DTB_ADDR: u64 = 0x88000000; // DTB load address
 pub const ROOT_ZONE_KERNEL_ADDR: u64 = 0x82000000; // kernel load address
@@ -119,6 +142,7 @@ pub const ROOT_ARCH_ZONE_CONFIG: HvArchZoneConfig = HvArchZoneConfig {
     gicv_size: 0x00000,
     gits_base: 0x1820000,
     gits_size: 0x10000,
+    is_aarch32: 0,
 };
 
 pub const ROOT_ZONE_IVC_CONFIG: [HvIvcConfig; 0] = [];

platform/aarch64/ok6254-c/cargo/features

@@ -1,3 +1,2 @@
 gicv3
 uart_16550
-uart_base_ok6254