riscv64: add aclint support

Cargo.toml

@@ -25,9 +25,11 @@ aarch64-cpu = "9.4.0"
 psci = { version = "0.1.0", default-features = false, features = ["smc"]}
 
 [target.'cfg(target_arch = "riscv64")'.dependencies]
-sbi-rt = { version = "0.0.2", features = ["legacy"] }
+sbi-rt = { version = "0.0.3", features = ["legacy"] }
 riscv = { git = "https://github.com/rcore-os/riscv", features = ["inline-asm"] }
 riscv-decode = "0.2.1"
+riscv-peripheral = "0.2.1"
+riscv-pac = "0.2.0"
 
 [target.'cfg(target_arch = "loongarch64")'.dependencies]
 loongArch64 = "0.2.4"
@@ -56,6 +58,7 @@ pt_layout_qemu = []
 # irqchip driver
 plic = []
 aia = []
+aclint = []
 ########### loongarch64 ############
 # irqchip driver
 loongson_7a2000 = []

platform/riscv64/qemu-aia/board.rs

@@ -2,6 +2,8 @@ use crate::{arch::zone::HvArchZoneConfig, config::*};
 
 pub const BOARD_NAME: &str = "qemu-aia";
 
+pub const ACLINT_SSWI_BASE: usize = 0x2F00000;
+
 pub const PLIC_BASE: usize = 0xc000000;
 pub const APLIC_BASE: usize = 0xc000000;
 pub const PLIC_MAX_IRQ: usize = 1024;

platform/riscv64/qemu-plic/board.rs

@@ -2,6 +2,8 @@ use crate::{arch::zone::HvArchZoneConfig, config::*};
 
 pub const BOARD_NAME: &str = "qem-plic";
 
+pub const ACLINT_SSWI_BASE: usize = 0x2F00000;
+
 pub const PLIC_BASE: usize = 0xc000000;
 pub const APLIC_BASE: usize = 0xc000000;
 pub const PLIC_MAX_IRQ: usize = 1024;
@@ -24,7 +26,7 @@ pub const ROOT_ZONE_MEMORY_REGIONS: [HvConfigMemoryRegion; 9] = [
         mem_type: MEM_TYPE_RAM,
         physical_start: 0x83000000,
         virtual_start: 0x83000000,
-        size: 0x1D000000,
+        size: 0x7D000000,
     }, // ram
     HvConfigMemoryRegion {
         mem_type: MEM_TYPE_IO,

platform/riscv64/qemu-plic/cargo/features

@@ -1 +1,2 @@
-plic
+plic
+aclint

platform/riscv64/qemu-plic/image/dts/zone0.dts

@@ -55,16 +55,26 @@
 
 	};
 
-	memory@83000000 {
+	memory@80000000 {
 		device_type = "memory";
-		reg = <0x0 0x83000000 0x0 0x1D000000>;
+		reg = <0x0 0x80000000 0x0 0x80000000>;
 	};
 
 	reserved-memory {
 		#address-cells = <0x02>;
 		#size-cells = <0x02>;
 		ranges;
 
+		opensbi@0x80000000 {
+			no-map;
+			reg = <0x00 0x80000000 0x00 0x00200000>;
+		};
+
+		hvisor@0x80200000 {
+			no-map;
+			reg = <0x00 0x80200000 0x00 0x02E00000>;
+		};
+
 		nonroot@0x83000000 {
 			no-map;
 			reg = <0x00 0x83000000 0x00 0x0C000000>;
@@ -81,6 +91,7 @@
 		#size-cells = <0x02>;
 		compatible = "simple-bus";
 		ranges;
+
 		plic: interrupt-controller@c000000 {
 			phandle = <0x03>;
 			riscv,ndev = <0x5f>;
@@ -94,46 +105,21 @@
 			compatible = "riscv,plic0";
 			#interrupt-cells = <0x1>;
 		};
+
 		uart@10000000 {
 			interrupts = <0x0a>;
 			interrupt-parent = <&plic>;
 			clock-frequency = "\08@";
 			reg = <0x00 0x10000000 0x00 0x100>;
 			compatible = "ns16550a";
 		};
-		pci@30000000 {
-			interrupt-map-mask = <0x1800 0x00 0x00 0x07>;
-			interrupt-map = <0x00 0x00 0x00 0x01 0x03 0x20 0x00 0x00 0x00 0x02 0x03 0x21 0x00 0x00 0x00 0x03 0x03 0x22 0x00 0x00 0x00 0x04 0x03 0x23 0x800 0x00 0x00 0x01 0x03 0x21 0x800 0x00 0x00 0x02 0x03 0x22 0x800 0x00 0x00 0x03 0x03 0x23 0x800 0x00 0x00 0x04 0x03 0x20 0x1000 0x00 0x00 0x01 0x03 0x22 0x1000 0x00 0x00 0x02 0x03 0x23 0x1000 0x00 0x00 0x03 0x03 0x20 0x1000 0x00 0x00 0x04 0x03 0x21 0x1800 0x00 0x00 0x01 0x03 0x23 0x1800 0x00 0x00 0x02 0x03 0x20 0x1800 0x00 0x00 0x03 0x03 0x21 0x1800 0x00 0x00 0x04 0x03 0x22>;
-			ranges = <0x1000000 0x00 0x00 0x00 0x3000000 0x00 0x10000 0x2000000 0x00 0x40000000 0x00 0x40000000 0x00 0x40000000 0x3000000 0x04 0x00 0x04 0x00 0x04 0x00>;
-			reg = <0x00 0x30000000 0x00 0x10000000>;
-			dma-coherent;
-			bus-range = <0x00 0xff>;
-			linux,pci-domain = <0x00>;
-			device_type = "pci";
-			compatible = "pci-host-ecam-generic";
-			#size-cells = <0x02>;
-			#interrupt-cells = <0x01>;
-			#address-cells = <0x03>;
-		};
 
 		virtio_mmio@10008000 {
-		interrupts = <0x8>;
-		interrupt-parent = <&plic>;
-		reg = <0x0 0x10008000 0x0 0x1000>;
-		compatible = "virtio,mmio";
+			interrupts = <0x8>;
+			interrupt-parent = <&plic>;
+			reg = <0x0 0x10008000 0x0 0x1000>;
+			compatible = "virtio,mmio";
 		};
-		//	virtio_mmio@10007000 {
-		//		interrupts = <0x7>;
-		//		interrupt-parent = <&plic>;
-		//		reg = <0x0 0x10007000 0x0 0x1000>;
-		//		compatible = "virtio,mmio";
-		//	};
-		// virtio_mmio@10006000 {
-		// 	interrupts = <0x6>;
-		// 	interrupt-parent = <&plic>;
-		// 	reg = <0x0 0x10006000 0x0 0x1000>;
-		// 	compatible = "virtio,mmio";
-		// };
 
 		virtio_mmio@10005000 {
 			interrupts = <0x5>;
@@ -173,5 +159,4 @@
 	chosen {
 		bootargs = "root=/dev/vda rw earlycon console=ttyS0";
 	};
-
 };

platform/riscv64/qemu-plic/platform.mk

@@ -10,11 +10,11 @@ zone0_dtb    := $(image_dir)/dts/zone0.dtb
 # zone1_kernel := $(image_dir)/kernel/Image
 # zone1_dtb    := $(image_dir)/devicetree/linux.dtb
 
-QEMU_ARGS := -machine virt
+QEMU_ARGS := -machine virt,aclint=on
 QEMU_ARGS += -bios default
 QEMU_ARGS += -cpu rv64
 QEMU_ARGS += -smp 4
-QEMU_ARGS += -m 2G
+QEMU_ARGS += -m 4G
 QEMU_ARGS += -nographic
 
 QEMU_ARGS += -kernel $(hvisor_bin)

src/arch/riscv64/ipi.rs

@@ -1,3 +1,10 @@
+use sbi_rt::HartMask;
+
+// arch_send_event
 pub fn arch_send_event(cpu_id: u64, _sgi_num: u64) {
-    sbi_rt::send_ipi(1 << cpu_id, 0);
+    info!("arch_send_event: cpu_id: {}", cpu_id);
+    #[cfg(feature = "aclint")]
+    crate::device::irqchip::aclint::aclint_send_ipi(cpu_id as usize);
+    #[cfg(not(feature = "aclint"))]
+    sbi_rt::send_ipi(HartMask::from_mask_base(1 << cpu_id, 0));
 }