cleanup: eliminate some warnings and clippy errors for aarch64

README-zh.md

@@ -39,7 +39,7 @@ hvisor 是一个用 Rust 实现的 Type-1 裸机虚拟机监控器，采用分
 |                    | imx-uart              | `aarch64`                | NXP i.MX8MP                     |
 |                    | NS16550A              | `loongarch64`            |                                 |
 |                    | xuartps               | `aarch64`                | Xilinx Ultrascale+ MPSoC ZCU102 |
-| **中断控制器**     | GIC irq controller    | `aarch64`                |                                 |
+| **中断控制器**     | GIC irq controller    | `aarch64`                | GICv2, GICv3                    |
 |                    | 7A2000 irq controller | `loongarch64`            |                                 |
 |                    | PLIC                  | `riscv64`                |                                 |
 |                    | AIA-APIC              | `riscv64`                | 仅支持 MSI 模式                 |

README.md

@@ -39,7 +39,7 @@ hvisor is a Type-1 bare-metal virtual machine monitor implemented in Rust, featu
 |                           | imx-uart              | `aarch64`                   | NXP i.MX8MP                     |
 |                           | NS16550A              | `loongarch64`               |                                 |
 |                           | xuartps               | `aarch64`                   | Xilinx Ultrascale+ MPSoC ZCU102 |
-| **Interrupt Controllers** | GIC irq controller    | `aarch64`                   |                                 |
+| **Interrupt Controllers** | GIC irq controller    | `aarch64`                   | GICv2, GICv3                    |
 |                           | 7A2000 irq controller | `loongarch64`               |                                 |
 |                           | PLIC                  | `riscv64`                   |                                 |
 |                           | AIA-APIC              | `riscv64`                   | Only supports MSI mode          |

src/arch/aarch64/cpu.rs

@@ -1,3 +1,6 @@
+#![allow(dead_code)]
+#![allow(unused_imports)]
+
 use crate::{
     arch::{mm::new_s2_memory_set, sysreg::write_sysreg},
     consts::{PAGE_SIZE, PER_CPU_ARRAY_PTR, PER_CPU_SIZE},

src/arch/aarch64/entry.rs

@@ -1,8 +1,7 @@
-use core::arch::global_asm;
+#![allow(unused)]
 
 use crate::consts::PER_CPU_SIZE;
-
-//global_asm!(include_str!("boot_pt.S"));
+use core::arch::global_asm;
 
 #[naked]
 #[no_mangle]

src/arch/aarch64/mm.rs

@@ -1,13 +1,13 @@
-use core::sync::atomic::AtomicU32;
+#![allow(unused)]
 
+use core::sync::atomic::AtomicU32;
 use spin::RwLock;
 
+use super::sysreg::read_sysreg;
 use crate::{
     arch::Stage2PageTable, consts::MAX_CPU_NUM, error::HvResult, memory::MemorySet, wait_for,
 };
 
-use super::sysreg::read_sysreg;
-
 pub fn init_hv_page_table() -> HvResult {
     todo!();
     // let mut hv_pt: MemorySet<Stage1PageTable> = MemorySet::new(4);

src/arch/aarch64/mmu.rs

@@ -1,3 +1,5 @@
+#![allow(unused)]
+
 use cfg_if::cfg_if;
 use cortex_a::registers::{MAIR_EL1, SCTLR_EL2};
 use tock_registers::interfaces::*;

src/arch/aarch64/mod.rs

@@ -1,3 +1,5 @@
+#![allow(unused_imports)]
+
 pub mod cpu;
 pub mod entry;
 pub mod iommu;

src/arch/aarch64/sysreg.rs

@@ -1,3 +1,5 @@
+#![allow(unused_imports)]
+
 // Copyright 2023 The arm-gic Authors.
 // This project is dual-licensed under Apache 2.0 and MIT terms.
 // See LICENSE-APACHE and LICENSE-MIT for details.

src/arch/aarch64/trap.rs

@@ -1,3 +1,5 @@
+#![allow(unused)]
+
 use aarch64_cpu::{asm::wfi, registers::*};
 use core::arch::global_asm;
 
@@ -395,7 +397,7 @@ fn handle_arch_smc(
         SMCccFnId::SMCCC_ARCH_FEATURES => !0,
         _ => {
             error!("unsupported ARM smc service");
-            return !0;
+            !0
         }
     }
 }

src/config.rs

@@ -1,3 +1,5 @@
+#![allow(unused)]
+
 use alloc::vec::Vec;
 use spin::Once;
 

src/device/irqchip/gicv3/gicr.rs

@@ -3,10 +3,10 @@
 // Copyright (c) 2020-2022 Andre Richter <[email protected]>
 
 //! GICC Driver - GIC CPU interface.
-
-use core::ptr;
+#![allow(unused)]
 
 use alloc::vec::Vec;
+use core::ptr;
 use spin::{mutex::Mutex, Once};
 
 use crate::{

src/device/irqchip/gicv3/mod.rs

@@ -76,29 +76,29 @@
 //!           - 00..15 SGIs
 //!           - 16..31 PPIs
 #![allow(dead_code)]
+#![allow(unused_imports)]
+
 pub mod gicd;
 pub mod gicr;
 pub mod gits;
 pub mod vgic;
 
+use alloc::collections::vec_deque::VecDeque;
+use alloc::vec::Vec;
 use core::arch::asm;
 use core::ptr::write_volatile;
 use core::sync::atomic::AtomicU64;
-
-use alloc::collections::btree_map::BTreeMap;
-use alloc::collections::vec_deque::VecDeque;
-use alloc::vec::Vec;
 use gicr::{init_lpi_prop, GICR_ISENABLER, GICR_SGI_BASE};
 use gits::gits_init;
 use spin::{Mutex, Once};
 
 use self::gicd::{enable_gic_are_ns, GICD_ICACTIVER, GICD_ICENABLER};
 use self::gicr::enable_ipi;
+
 use crate::arch::aarch64::sysreg::{read_sysreg, smc_arg1, write_sysreg};
 use crate::arch::cpu::this_cpu_id;
 use crate::config::root_zone_config;
 use crate::consts::MAX_CPU_NUM;
-
 use crate::event::check_events;
 use crate::hypercall::SGI_IPI_ID;
 use crate::zone::Zone;
@@ -374,7 +374,7 @@ pub fn inject_irq(irq_id: usize, is_hardware: bool) -> bool {
             .add_irq(irq_id, is_hardware)
             .unwrap();
         enable_maintenace_interrupt(true);
-        return false;
+        false
     } else {
         let mut val = irq_id as u64; //v intid
         val |= 1 << 60; //group 1
@@ -385,7 +385,7 @@ pub fn inject_irq(irq_id: usize, is_hardware: bool) -> bool {
             val |= (irq_id as u64) << 32; //pINTID
         }
         write_lr(free_ir as usize, val);
-        return true;
+        true
     }
 }
 

src/device/uart/mod.rs

@@ -1,3 +1,5 @@
+#![allow(unused_imports)]
+
 #[cfg(all(feature = "platform_qemu", target_arch = "aarch64"))]
 mod pl011;
 

src/device/virtio_trampoline.rs

@@ -24,6 +24,7 @@ pub static VIRTIO_BRIDGE: Mutex<VirtioBridgeRegion> = Mutex::new(VirtioBridgeReg
 const QUEUE_NOTIFY: usize = 0x50;
 pub const MAX_REQ: u32 = 32;
 pub const MAX_DEVS: usize = 4; // Attention: The max virtio-dev number for vm is 4.
+#[allow(unused)]
 pub const MAX_CPUS: usize = 4;
 pub const IRQ_WAKEUP_VIRTIO_DEVICE: usize = 32 + 0x20;
 
@@ -75,6 +76,7 @@ pub fn mmio_virtio_handler(mmio: &mut MMIOAccess, base: usize) -> HvResult {
     if need_interrupt == 0 {
         // when virtio backend finish the req, it will add 1 to cfg_flag.
         while cfg_flags[cpu_id] == old_cfg_flag {
+            // TODO: fix the clippy: this may lead to an infinite or to a never running loop
             // fence(Ordering::Acquire);
             count += 1;
             if count > 1000000 {

src/event.rs

@@ -1,7 +1,9 @@
+#![allow(unused)]
+
 use crate::{
     arch::ipi::arch_send_event,
     device::{
-        irqchip::{self, inject_irq},
+        irqchip::inject_irq,
         virtio_trampoline::{handle_virtio_irq, IRQ_WAKEUP_VIRTIO_DEVICE},
     },
     percpu::this_cpu_data,
@@ -113,7 +115,7 @@ pub fn check_events() -> bool {
         }
         #[cfg(target_arch = "loongarch64")]
         Some(IPI_EVENT_CLEAR_INJECT_IRQ) => {
-            irqchip::ls7a2000::clear_hwi_injected_irq();
+            crate::device::irqchip::ls7a2000::clear_hwi_injected_irq();
             true
         }
         _ => false,

src/hypercall/mod.rs

@@ -1,16 +1,16 @@
 #![allow(dead_code)]
+#![allow(unused_imports)]
 use crate::arch::cpu::this_cpu_id;
 use crate::config::HvZoneConfig;
 use crate::consts::{INVALID_ADDRESS, MAX_CPU_NUM, PAGE_SIZE};
 use crate::device::irqchip::inject_irq;
 use crate::device::virtio_trampoline::{MAX_DEVS, MAX_REQ, VIRTIO_BRIDGE, VIRTIO_IRQS};
 use crate::error::HvResult;
+use crate::event::{send_event, IPI_EVENT_SHUTDOWN, IPI_EVENT_VIRTIO_INJECT_IRQ, IPI_EVENT_WAKEUP};
 use crate::percpu::{get_cpu_data, this_zone, PerCpu};
 use crate::zone::{
     all_zones_info, find_zone, is_this_root_zone, remove_zone, this_zone_id, zone_create, ZoneInfo,
 };
-
-use crate::event::{send_event, IPI_EVENT_SHUTDOWN, IPI_EVENT_VIRTIO_INJECT_IRQ, IPI_EVENT_WAKEUP};
 use core::convert::TryFrom;
 use core::sync::atomic::{fence, Ordering};
 
@@ -79,6 +79,7 @@ impl<'a> HyperCall<'a> {
                 }
                 #[cfg(target_arch = "aarch64")]
                 HyperCallCode::HvIvcInfo => self.hv_ivc_info(arg0),
+                #[allow(unreachable_patterns)]
                 _ => {
                     warn!("hypercall id={} unsupported!", code as u64);
                     Ok(0)

src/ivc.rs

@@ -1,9 +1,7 @@
-use core::ptr::write_volatile;
+#![allow(unused)]
 
-use alloc::{
-    collections::{btree_map::BTreeMap, btree_set::BTreeSet},
-    vec::Vec,
-};
+use alloc::collections::btree_map::BTreeMap;
+use core::ptr::write_volatile;
 use spin::Mutex;
 
 use crate::device::irqchip::set_ispender;

src/main.rs

@@ -50,6 +50,8 @@ mod zone;
 mod ivc;
 
 mod pci;
+
+#[cfg(test)]
 mod tests;
 
 #[cfg(target_arch = "aarch64")]

src/memory/addr.rs

@@ -2,8 +2,6 @@
 
 #![allow(dead_code)]
 
-use core::fmt::Debug;
-
 use crate::consts::PAGE_SIZE;
 
 pub type VirtAddr = usize;

src/memory/mapper.rs

@@ -39,7 +39,6 @@ impl<VA: From<usize> + Into<usize> + Copy> MemoryRegion<VA> {
         flags: MemFlags,
     ) -> Self {
         let start_vaddr = start_vaddr.into();
-        let start_paddr = start_paddr;
         // bug: vaddr > paddr?
         let phys_virt_offset = start_vaddr.wrapping_sub(start_paddr);
         Self::new(

src/memory/mmio.rs

@@ -1,8 +1,6 @@
-use core::ptr;
-
-use crate::{error::HvResult, percpu::this_zone};
-
 use super::GuestPhysAddr;
+use crate::{error::HvResult, percpu::this_zone};
+use core::ptr;
 
 pub type MMIOHandler = fn(&mut MMIOAccess, usize) -> HvResult;
 
@@ -77,6 +75,7 @@ pub fn mmio_handle_access(mmio: &mut MMIOAccess) -> HvResult {
     }
 }
 
+#[allow(unused)]
 pub fn mmio_generic_handler(mmio: &mut MMIOAccess, base: usize) -> HvResult {
     mmio_perform_access(base, mmio);
     Ok(())

src/memory/mod.rs

@@ -1,3 +1,5 @@
+#![allow(unused)]
+
 pub mod addr;
 pub mod frame;
 pub mod heap;

src/panic.rs

@@ -1,4 +1,8 @@
+#![allow(unused_imports)]
+
+#[cfg(test)]
 use crate::tests::*;
+
 use core::panic::PanicInfo;
 
 #[panic_handler]

src/pci/endpoint.rs

@@ -14,8 +14,7 @@ pub struct EndpointConfig {
 impl EndpointConfig {
     pub fn new(bdf: usize) -> Self {
         let (bars, bdf) = { ([PciBar::default(); NUM_BAR_REGS_TYPE0], bdf) };
-        let r = EndpointConfig { bars, bdf };
-        r
+        EndpointConfig { bars, bdf }
     }
 
     pub fn bars_init(&mut self, bar_id: usize, origin_val: u32, val: u32) {

src/pci/pci.rs

@@ -1,3 +1,6 @@
+#![allow(unused_imports)]
+
+use alloc::vec::Vec;
 use core::{ptr, usize};
 
 use crate::config::{HvPciConfig, CONFIG_MAX_PCI_DEV};
@@ -12,7 +15,6 @@ use crate::{
     memory::{mmio_perform_access, GuestPhysAddr, MemFlags, MemoryRegion},
     zone::Zone,
 };
-use alloc::vec::Vec;
 
 use super::bridge::BridgeConfig;
 use super::endpoint::EndpointConfig;

src/percpu.rs

@@ -1,17 +1,14 @@
 use alloc::sync::Arc;
-use alloc::vec::Vec;
 use spin::{Mutex, RwLock};
 
 use crate::arch::cpu::{this_cpu_id, ArchCpu};
 use crate::consts::{INVALID_ADDRESS, PER_CPU_ARRAY_PTR, PER_CPU_SIZE};
 use crate::memory::addr::VirtAddr;
 use crate::zone::Zone;
-use crate::{arch, ENTERED_CPUS};
+use crate::ENTERED_CPUS;
 use core::fmt::Debug;
 use core::sync::atomic::Ordering;
 
-// global_asm!(include_str!("./arch/aarch64/page_table.S"),);
-
 #[cfg(test)]
 mod tests;
 

src/percpu/tests.rs

@@ -1,4 +1,5 @@
 use super::*;
+use alloc::vec::Vec;
 
 #[test_case]
 fn test_cpuset() {

src/platform/mod.rs

@@ -1,3 +1,5 @@
+#![allow(unused_assignments)]
+
 use crate::{
     config::{
         HvConfigMemoryRegion, HvIvcConfig, HvPciConfig, HvZoneConfig, CONFIG_MAX_INTERRUPTS,

src/tests.rs

@@ -1,3 +1,5 @@
+#![allow(unused)]
+
 /// this module is for unittests of hvisor
 /// since this is a baremetal program
 /// all unittests are performed when running hvisor on qemu