milestone hvisor v0.1.0 #106
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Remove CLI, Virtio daemon and kernel module
* add riscv kernel&rootfs * riscv boot root linux * add cpu parking page (riscv) * test hypercall HvZoneStart
* change each vm's ram to 1G * test notify before * support riscv hvisor-tool
leave all inteface functions as todo!()
merge local hvisor loongarch port to syswonder/hvisor dev-loongarch branch
fix: change data type to prevent potential hvisor-daemon startup failure
Modify hvisor(riscv64) to adapt hvisor-tool config
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need a changelog.md or CHANGES file in the root directory, specifying each the features of each version. |
…ors and modify riscv64 support entry author
Contributor
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Please wait pr #78 merged to dev. |
enkerewpo
added
documentation
enkerewpo
changed the title
* Add AIA and Solve the problem of TAB completion * add aia=aplic-imsic * add aia * Standardize riscv-aia FEATURES * Standardize the annotation.
Update author information in various files to reflect new email address Update runner path in cargo config and change default features to gicv3 Update CI workflow to disable fail-fast and comment out riscv64 support for future implementation Update CI workflow to use rustc_target for target specification Update CI workflow to include rustc_target for aarch64 and riscv64 architectures Update CI workflow to improve test matrix structure and naming Refactor code for consistency and readability by adjusting formatting and removing unnecessary whitespace
Add changelog, updated Github CI and formatted exisiting code with cargo fmt
KouweiLee
approved these changes
Feb 28, 2025
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#105