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@jserv jserv commented Sep 21, 2025

The JIT compiler was experiencing intermittent failures on Arm64 / Apple Silicon due to missing instruction cache invalidation after patching branch instructions. When update_branch_imm() modified branch targets in JIT-compiled code, the CPU's instruction cache was not being invalidated, causing it to execute stale cached instructions instead of the newly patched ones.

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Benchmarks

Benchmark suite Current: ef57d84 Previous: 9ba5553 Ratio
Dhrystone 1333 Average DMIPS over 10 runs 1323 Average DMIPS over 10 runs 0.99
Coremark 957.852 Average iterations/sec over 10 runs 906.292 Average iterations/sec over 10 runs 0.95

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@jserv jserv force-pushed the fix-regressions branch 10 times, most recently from 879d4eb to a568fcf Compare September 22, 2025 17:24
@jserv jserv changed the title Fix regressions Fix T2C race conditions Sep 22, 2025
@jserv jserv force-pushed the fix-regressions branch 7 times, most recently from 2852a99 to 77e4f83 Compare September 24, 2025 19:39
@jserv jserv changed the title Fix T2C race conditions Attempt to fix JIT instruction cache coherency on Arm64 Sep 24, 2025
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@jserv jserv force-pushed the fix-regressions branch 2 times, most recently from 6df6884 to 3340a9b Compare September 24, 2025 21:40
@jserv jserv force-pushed the fix-regressions branch 19 times, most recently from 84ab530 to 786e15e Compare September 26, 2025 04:26
This addresses critical issues in the JIT compiler that caused failures,
particularly noticeable when ENABLE_EXT_F=0:
1. Check translation success before execution: The emulator now verifies
   that jit_translate() successfully marked a block as "hot" before
   attempting to execute the JIT-compiled code. This prevents execution
   of incomplete or failed translations.
2. Reset jump count on cache flush: The state->n_jumps counter was not
   being reset during code_cache_flush(), causing stale jump entries to
   persist and corrupt subsequent translations.
3. Mark incomplete translations properly: When a cache flush occurs
   mid-translation, the block is now correctly marked as not hot,
   ensuring it won't be mistakenly executed as valid JIT code.

These fixes resolve the non-deterministic test failures observed in
the pi calculation test and other compute-intensive benchmarks.
- Move pthread_jit_write_protect_np(false) before reading MAP_JIT memory
  in update_branch_imm since Apple Silicon requires write mode for both
  read and write operations on MAP_JIT memory
- Add missing cache invalidation in resolve_jumps() for x86_64 after
  patching jump offsets
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