fix ai fu types mapping

ai_assistant_sample/ai_assistant.py

@@ -52,14 +52,20 @@
 7. If goal is 'low_power': prefer smaller area, lower memory usage, balanced FU count.
 
 ## Available FU Types (for tile configuration):
-- Compute: add, mul, div, shift, logic
-- Floating-point: fadd, fmul, fdiv, fmul_fadd, fadd_fadd, vfmul
-- Control: cmp, sel, phi, loop_control
-- Memory: mem, mem_indexed, constant
-- Other: return, grant, alloca, type_conv
+- Integer Arithmetic: alu (add/sub), mul, div, shift, mac
+- Logic: logic (and/or/not/xor), cmp (icmp/fcmp), sel
+- Floating-point: fadd, fmul, fdiv, fmul_fadd, fadd_fadd
+- Memory: mem (load/store), mem_indexed, alloca, gep, memset
+- Type: type_conv, constant
+- Control: phi, return, branch, loop_control
+- Data Movement: data_mov, ctrl_mov, reserve, data
+- Grants: grant
+- Vector: vadd, vmul, vfmul, vector
 
 IMPORTANT: By default, all FU types should be enabled in every tile whenever we design a CGRA.
-The full FU list is: ["add", "mul", "div", "fadd", "fmul", "fdiv", "logic", "cmp", "sel", "type_conv", "vfmul", "fadd_fadd", "fmul_fadd", "loop_control", "phi", "constant", "mem", "mem_indexed", "shift", "return", "alloca", "grant"]
+The full FU list is: ["alu", "mul", "div", "shift", "mac", "logic", "cmp", "sel", "fadd", "fmul", "fdiv", "fmul_fadd", "fadd_fadd", "mem", "mem_indexed", "alloca", "gep", "memset", "type_conv", "constant", "phi", "return", "branch", "loop_control", "data_mov", "ctrl_mov", "reserve", "data", "grant", "vadd", "vmul", "vfmul", "vector"]
+IMPORTANT: Use exactly these FU names. Do NOT use instruction names (e.g., use "alu" not "add", use "mem" not "load").
+For low_power designs, you may remove some FUs, but ALWAYS keep at minimum: alu, mul, cmp, sel, phi, constant, mem, gep, return, branch, data_mov, ctrl_mov, reserve, data, grant
 
 When recommending CGRA configurations, provide THREE options:
 
@@ -72,7 +78,7 @@
     "data_spm_kb": <4-64>,
     "multi_cgra_rows": <1-4>,
     "multi_cgra_columns": <1-4>,
-    "fu_types": ["add", "mul", "div", ...],
+    "fu_types": ["alu", "mul", "div", ...],
     "explanation": "<high_performance optimization reasoning>"
   },
   "balanced": {
@@ -82,7 +88,7 @@
     "data_spm_kb": <4-64>,
     "multi_cgra_rows": <1-4>,
     "multi_cgra_columns": <1-4>,
-    "fu_types": ["add", "mul", ...],
+    "fu_types": ["alu", "mul", ...],
     "explanation": "<balanced trade-off reasoning>"
   },
   "low_power": {
@@ -92,7 +98,7 @@
     "data_spm_kb": <4-64>,
     "multi_cgra_rows": <1-4>,
     "multi_cgra_columns": <1-4>,
-    "fu_types": ["add", "mul", ...],
+    "fu_types": ["alu", "mul", ...],
     "explanation": "<power saving reasoning>"
   }
 }
@@ -127,18 +133,15 @@
 # Kernel examples with DFG characteristics and recommended configurations
 
 ALL_FU_TYPES = [
-    "add", "mul", "div",
-    "fadd", "fmul", "fdiv",
+    "alu", "mul", "div", "shift", "mac",
     "logic", "cmp", "sel",
-    "type_conv",
-    "vfmul",
-    "fadd_fadd", "fmul_fadd",
-    "loop_control", "phi",
-    "constant",
-    "mem", "mem_indexed",
-    "shift",
-    "return", "alloca",
+    "fadd", "fmul", "fdiv", "fmul_fadd", "fadd_fadd",
+    "mem", "mem_indexed", "alloca", "gep", "memset",
+    "type_conv", "constant",
+    "phi", "return", "branch", "loop_control",
+    "data_mov", "ctrl_mov", "reserve", "data",
     "grant",
+    "vadd", "vmul", "vfmul", "vector",
 ]
 
 RAG_KERNEL_DATABASE = {

cgra-flow-docker/Dockerfile

@@ -115,8 +115,8 @@ RUN cmake -G Ninja .. \
 
 WORKDIR /cgra
 
-# Clone VectorCGRA
-RUN git clone https://github.com/tancheng/VectorCGRA.git
+# Clone VectorCGRA with submodules
+RUN git clone --recursive https://github.com/tancheng/VectorCGRA.git
 
 # Set up Python virtual environment and install dependencies
 RUN python3.12 -m venv /cgra/venv
@@ -131,7 +131,8 @@ RUN pip install --upgrade pip && \
     pip install -U git+https://github.com/tancheng/pymtl3.1@yo-struct-list-fix && \
     pip install hypothesis && \
     pip install pytest && \
-    pip install py-markdown-table
+    pip install py-markdown-table && \
+    pip install pyyaml
 
 # Set default working directory
 WORKDIR /cgra

openspec/changes/add-verification-page-modules/.openspec.yaml

@@ -0,0 +1,2 @@
+schema: spec-driven
+created: 2026-03-02

openspec/changes/add-verification-page-modules/design.md

@@ -0,0 +1,68 @@
+## Context
+
+`VerificationTab.jsx` currently renders a static "Under Construction" placeholder. The verification stage is the final step in the CGRA workflow (after Design → Mapping), and users expect to review test results, inspect generated SVerilog, and examine area/power data there. This change delivers the UI scaffold for those three panels, with mocked/static data, so the layout and interaction patterns are established before backend integration.
+
+The project uses React 19 + MUI 7 with a tab-panel architecture. Other tabs (`MappingTab.jsx`, `DesignTab.jsx`) use a combination of MUI `Box`, `Paper`, `Typography`, and layout components — the same patterns apply here.
+
+## Goals / Non-Goals
+
+**Goals:**
+- Replace the placeholder in `VerificationTab.jsx` with a three-panel layout
+- Implement `TestsPanel`: list of test cases with status icons (pass/fail/pending)
+- Implement `SverilogPanel`: read-only code viewer for SystemVerilog source
+- Implement `ReportPanel`: area and power metrics in a structured table/card
+- Use mocked static data for all panels (no API calls)
+- Follow existing MUI + functional-component conventions
+
+**Non-Goals:**
+- Backend integration or real data fetching
+- Running actual tests from the UI
+- Editing or downloading SVerilog source
+- Exporting report data
+- Playwright E2E tests for this change (UI-only, no functional behavior)
+
+## Decisions
+
+### Decision: Separate sub-components vs. inline in VerificationTab
+
+**Choice**: Extract each panel into its own file under `src/workspace/verification/`.
+
+**Rationale**: `MappingTab.jsx` is 400+ lines and already complex with inline sub-sections. Keeping each panel in its own file (`TestsPanel.jsx`, `SverilogPanel.jsx`, `ReportPanel.jsx`) makes future backend wiring straightforward — each file has a clear responsibility and a single import point. The change stays small and reviewable.
+
+**Alternative considered**: Inline everything in `VerificationTab.jsx`. Rejected because it creates a monolithic file and makes incremental backend addition harder.
+
+### Decision: Layout — vertical stack of collapsible panels
+
+**Choice**: Use MUI `Accordion` components stacked vertically, one per panel, with the first panel (`Tests`) expanded by default.
+
+**Rationale**: Three peer panels compete for vertical space. Accordions let the user focus on one panel at a time without scrolling. This mirrors patterns used in common IDEs and the existing Property Inspector sidebar. MUI `Accordion` is already available in the dependency set.
+
+**Alternative considered**: Fixed 3-column horizontal split. Rejected because SVerilog code and test lists are both tall content that reads poorly in narrow columns on typical monitor widths.
+
+### Decision: SVerilog display — `<pre>` / monospace box, no syntax highlighter library
+
+**Choice**: Render SVerilog inside a scrollable MUI `Box` with `fontFamily: 'monospace'` styling and a dark background, with no third-party syntax highlighter.
+
+**Rationale**: Adding a syntax-highlighting library (e.g., `react-syntax-highlighter`, `shiki`) is a new dependency that requires team review. Since this is a UI-scaffold change with mocked data, a styled `<pre>` block is sufficient to validate the layout without dependency risk.
+
+**Alternative considered**: `react-syntax-highlighter`. Deferred to a future backend-integration change.
+
+### Decision: Mocked data co-located in each panel component
+
+**Choice**: Each panel defines its own `MOCK_*` constant at the top of its file.
+
+**Rationale**: Keeps the mock easy to locate and replace when real data arrives. The mock shapes the component's prop interface, so when a parent passes real data the panel just needs a `data` prop swap.
+
+## Risks / Trade-offs
+
+- **Risk**: Accordion default-expand behaviour may feel unexpected if users expect all panels visible at once. → **Mitigation**: Default-expand "Tests" only; document in the component JSDoc that the expand state is uncontrolled and can be made controlled when data is wired up.
+- **Risk**: Monospace box without line numbers may be hard to navigate for long SVerilog files. → **Mitigation**: Acceptable for the mocked-data phase; add line numbers when real output is integrated.
+- **Trade-off**: Three new files adds a small directory to maintain, but the isolation benefit outweighs the overhead.
+
+## Migration Plan
+
+1. Create `src/workspace/verification/` directory
+2. Create `TestsPanel.jsx`, `SverilogPanel.jsx`, `ReportPanel.jsx` with mocked data
+3. Update `VerificationTab.jsx` to import and render all three panels inside MUI Accordions
+4. Verify visually via `npm run dev`
+5. No rollback concern — change is additive, placeholder is trivially restorable

openspec/changes/add-verification-page-modules/proposal.md

@@ -0,0 +1,31 @@
+## Why
+
+The Verification tab currently shows an "Under Construction" placeholder with no functional UI. Users completing a mapping workflow have no place to view test results, inspect generated SVerilog, or review area/power report data for their CGRA design. Adding structured UI panels to this tab makes the verification stage a first-class step in the workflow.
+
+## What Changes
+
+- Replace the placeholder content in `VerificationTab.jsx` with a three-panel layout
+- Add a **Tests** panel: displays a list of test cases with their pass/fail status indicators
+- Add a **SVerilog** panel: shows the generated SystemVerilog source in a read-only code viewer (syntax-highlighted)
+- Add a **Report Area/Power** panel: presents area and power metrics in a structured table or card layout
+- All panels are UI-only; data is static/mocked — no backend integration in this change
+
+## Capabilities
+
+### New Capabilities
+
+- `verification-tests-panel`: Test-case list UI inside the Verification tab, showing test names and pass/fail status
+- `verification-sverilog-panel`: Read-only SVerilog code viewer inside the Verification tab
+- `verification-report-panel`: Area and power metrics display panel inside the Verification tab
+
+### Modified Capabilities
+
+*(none — no existing spec-level requirements are changing)*
+
+## Impact
+
+- **Modified file**: `src/workspace/VerificationTab.jsx` — replaces placeholder with three-panel layout
+- **Possible new components**: `src/workspace/verification/TestsPanel.jsx`, `SverilogPanel.jsx`, `ReportPanel.jsx` (or inlined in VerificationTab)
+- **Dependencies**: MUI components already available; no new npm packages required
+- **No backend changes**, no API changes, no auth changes
+- **No breaking changes**

openspec/changes/add-verification-page-modules/specs/verification-report-panel/spec.md

@@ -0,0 +1,20 @@
+## ADDED Requirements
+
+### Requirement: Report panel displays area and power metrics
+The Verification tab SHALL include a Report Area/Power panel that presents CGRA area and power metrics in a structured table layout.
+
+#### Scenario: Report panel is visible on the Verification tab
+- **WHEN** the user opens the Verification tab
+- **THEN** the Report Area/Power panel SHALL be present as a collapsible accordion section with the title "Report Area/Power"
+
+#### Scenario: Metrics table renders rows for area and power
+- **WHEN** the Report panel is expanded
+- **THEN** the panel SHALL display a table with at least the following metric rows: Total Area, Cell Area, Net Area, Total Power, Dynamic Power, and Leakage Power
+
+#### Scenario: Each metric row shows a name and value
+- **WHEN** a metric row is rendered
+- **THEN** it SHALL display the metric name in the first column and the metric value (with unit, e.g. "µm²" or "mW") in the second column
+
+#### Scenario: Mocked data is shown when no real report is available
+- **WHEN** the Verification tab is opened without a completed synthesis run
+- **THEN** the Report panel SHALL still render with placeholder/mocked values rather than showing an error or empty state

openspec/changes/add-verification-page-modules/specs/verification-sverilog-panel/spec.md

@@ -0,0 +1,20 @@
+## ADDED Requirements
+
+### Requirement: SVerilog panel displays generated SystemVerilog source
+The Verification tab SHALL include an SVerilog panel that renders the generated SystemVerilog source code in a read-only, scrollable, monospace code viewer.
+
+#### Scenario: SVerilog panel is visible on the Verification tab
+- **WHEN** the user opens the Verification tab
+- **THEN** the SVerilog panel SHALL be present as a collapsible accordion section with the title "SVerilog"
+
+#### Scenario: Code is displayed in monospace font with dark background
+- **WHEN** the SVerilog panel is expanded
+- **THEN** the code content SHALL be rendered in a monospace font inside a dark-background scrollable container
+
+#### Scenario: Code is read-only
+- **WHEN** the user attempts to interact with the code viewer
+- **THEN** the content SHALL NOT be editable (rendered as `<pre>` or equivalent non-editable element)
+
+#### Scenario: Long source scrolls vertically
+- **WHEN** the SVerilog content exceeds the panel's visible height
+- **THEN** a vertical scrollbar SHALL appear and the content SHALL be fully accessible by scrolling

openspec/changes/add-verification-page-modules/specs/verification-tests-panel/spec.md

@@ -0,0 +1,20 @@
+## ADDED Requirements
+
+### Requirement: Tests panel displays test case list
+The Verification tab SHALL include a Tests panel that renders a scrollable list of test cases. Each test case entry SHALL display the test name and a status indicator.
+
+#### Scenario: Test list renders with mocked data
+- **WHEN** the user opens the Verification tab
+- **THEN** the Tests panel SHALL be visible and expanded by default, showing at least one test case entry with a name and status icon
+
+#### Scenario: Passed test case appearance
+- **WHEN** a test case has status "pass"
+- **THEN** its status indicator SHALL use a green check-circle icon (MUI `CheckCircleIcon` with `color="success"`)
+
+#### Scenario: Failed test case appearance
+- **WHEN** a test case has status "fail"
+- **THEN** its status indicator SHALL use a red error icon (MUI `ErrorIcon` with `color="error"`)
+
+#### Scenario: Pending test case appearance
+- **WHEN** a test case has status "pending"
+- **THEN** its status indicator SHALL use a grey hourglass icon (MUI `HourglassEmptyIcon` with `color="disabled"`)

openspec/changes/add-verification-page-modules/tasks.md

@@ -0,0 +1,51 @@
+## 1. Directory & File Scaffold
+
+- [x] 1.1 Create directory `src/workspace/verification/`
+- [x] 1.2 Create empty file `src/workspace/verification/TestsPanel.jsx`
+- [x] 1.3 Create empty file `src/workspace/verification/SverilogPanel.jsx`
+- [x] 1.4 Create empty file `src/workspace/verification/ReportPanel.jsx`
+
+## 2. TestsPanel Implementation
+
+- [x] 2.1 Define `MOCK_TESTS` array in `TestsPanel.jsx` with at least 5 test cases covering `pass`, `fail`, and `pending` statuses
+- [x] 2.2 Implement the list layout using MUI `List` / `ListItem` components, one row per test case
+- [x] 2.3 Render status icon per test: `CheckCircleIcon` (success) for pass, `ErrorIcon` (error) for fail, `HourglassEmptyIcon` (disabled) for pending
+- [x] 2.4 Display test name as `Typography` `body2` next to the status icon
+- [x] 2.5 Make the list scrollable (set `overflow: 'auto'` and a `maxHeight` on the container)
+- [x] 2.6 Export `TestsPanel` as default export
+
+## 3. SverilogPanel Implementation
+
+- [x] 3.1 Define `MOCK_SVERILOG` string constant in `SverilogPanel.jsx` containing a representative multi-line SystemVerilog snippet (module declaration, ports, logic)
+- [x] 3.2 Render the code in a MUI `Box` with `component="pre"`, `fontFamily: 'monospace'`, dark background (`background: '#1e1e1e'`, `color: '#d4d4d4'`), and `overflow: 'auto'`
+- [x] 3.3 Set a fixed `maxHeight` (e.g., `400px`) so the panel doesn't expand infinitely
+- [x] 3.4 Confirm the container is non-editable (use `<pre>` / `contentEditable` not set)
+- [x] 3.5 Export `SverilogPanel` as default export
+
+## 4. ReportPanel Implementation
+
+- [x] 4.1 Define `MOCK_REPORT_ROWS` array in `ReportPanel.jsx` with entries for: Total Area, Cell Area, Net Area, Total Power, Dynamic Power, Leakage Power — each with a `label`, `value`, and `unit` field
+- [x] 4.2 Render a MUI `Table` with two columns: "Metric" and "Value"
+- [x] 4.3 Map `MOCK_REPORT_ROWS` to `TableRow` elements; display `label` in column 1 and `${value} ${unit}` in column 2
+- [x] 4.4 Add a `TableHead` row with column labels ("Metric", "Value") styled with `fontWeight: 'bold'`
+- [x] 4.5 Wrap the table in `TableContainer` with `Paper` for visual grouping
+- [x] 4.6 Export `ReportPanel` as default export
+
+## 5. VerificationTab Integration
+
+- [x] 5.1 Import `Accordion`, `AccordionSummary`, `AccordionDetails`, and `ExpandMoreIcon` from MUI in `VerificationTab.jsx`
+- [x] 5.2 Import `TestsPanel`, `SverilogPanel`, and `ReportPanel` from the `./verification/` directory
+- [x] 5.3 Remove the existing placeholder (`ConstructionIcon` + Under Construction text)
+- [x] 5.4 Render three `Accordion` panels stacked vertically inside a scrollable `Box`:
+  - Accordion 1: summary "Tests", `defaultExpanded={true}`, content `<TestsPanel />`
+  - Accordion 2: summary "SVerilog", content `<SverilogPanel />`
+  - Accordion 3: summary "Report Area/Power", content `<ReportPanel />`
+- [x] 5.5 Style each `AccordionSummary` title with `Typography variant="subtitle1" fontWeight="bold"`
+
+## 6. Visual Verification
+
+- [x] 6.1 Run `npm run dev` and open the app in a browser
+- [ ] 6.2 Navigate to the Verification tab and confirm all three accordions are visible
+- [ ] 6.3 Confirm "Tests" accordion is expanded by default on load
+- [ ] 6.4 Expand the SVerilog accordion and confirm monospace code is readable and scrollable
+- [ ] 6.5 Expand the Report accordion and confirm the two-column metric table renders correctly

openspec/changes/fix-ai-fu-types-mapping/.openspec.yaml

@@ -0,0 +1,2 @@
+schema: spec-driven
+created: 2026-02-27

openspec/changes/verification-sverilog-panel/.openspec.yaml

@@ -0,0 +1,2 @@
+schema: spec-driven
+created: 2026-03-02