MIPS32_Inorder_Processor

MIPS 32 Processor

The MIPS 32 In order 5 stage Pipeline. As part of NPTEL Verilog Course (Week 8 :: Link : https://archive.nptel.ac.in/courses/106/105/106105165/ to https://archive.nptel.ac.in/courses/106/105/106105165/) this project was discussed which givs basic insight of RTL Verilog coding style, basic computer architecture : Pipeline Module.

The concepts learnt in this are :

1. The MIPS32 Instruction Set Architecture (ISA).
2. MIPS32 Instruction encoding and different Instructions syntax.
3. MIPS32 Addressing Modes.
4. In-Order 5 stage Pipeline : Instruction Fetch, Decode, Execute, Register Write and Write back stage.
5. The Pipeline hazards found in In-Order Pipeline.
6. Illustrate an example of MIPS32 program. Executing the testbench and simulation results discussion.