Add TI DRV8846 support

Documentation/devicetree/bindings/pwm/ti,drv8846.yaml

@@ -0,0 +1,160 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pwm/ti,drv8846.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: TI DRV8846 Dual H-Bridge Stepper Motor Controller
+
+description: |
+  The DRV8846 is a stepper motor driver which contains two identical
+  H-bridge motor drivers with current-control PWM circuitry.
+
+  See https://www.ti.com/lit/ds/symlink/drv8846.pdf for more details.
+
+maintainers:
+  - Stanislaw <[email protected]>
+
+properties:
+  compatible:
+    const: ti,drv8846
+
+  pwms:
+    maxItems: 1
+
+  iscal0-gpio:
+    $ref: /schemas/types.yaml#/definitions/phandle-array
+    description: |
+        Torque DAC current scalar for pin I0.
+        Scales the current from 100% to 12.5% in 12.5% steps; tri-level pin.
+
+  iscal1-gpio:
+    $ref: /schemas/types.yaml#/definitions/phandle-array
+    description: |
+        Torque DAC current scalar for pin I1.
+        Scales the current from 100% to 12.5% in 12.5% steps; tri-level pin.
+
+  mode0-gpio:
+    $ref: /schemas/types.yaml#/definitions/phandle-array
+    description: |
+        Microstepping mode setting pin M0.
+        Controls step mode (full, half, up to 1/32-step) and single- or dual-
+        edge clocking; tri-level pin.
+
+  mode1-gpio:
+    $ref: /schemas/types.yaml#/definitions/phandle-array
+    description: |
+        Microstepping mode setting pin M1.
+        Controls step mode (full, half, up to 1/32-step) and single- or dual-
+        edge clocking; tri-level pin.
+
+  sleep-gpio:
+    $ref: /schemas/types.yaml#/definitions/phandle-array
+    description: |
+        Sleep mode input.
+        Logic high to enable device; logic low to enter low-power sleep mode;
+        internal pulldown.
+
+  adec-gpio:
+    $ref: /schemas/types.yaml#/definitions/phandle-array
+    description: |
+        Smart tune enable.
+        Logic low sets decay modes by DEC0 and DEC1 pins; logic high –
+        smart tune operation is enabled; must be set prior to coming out of
+        sleep; internal pulldown.
+
+  dec0-gpio:
+    $ref: /schemas/types.yaml#/definitions/phandle-array
+    description: |
+        Decay mode setting pin DEC0.
+        Controls decay mode (supports fast, slow, mixed, and smart tune modes).
+
+  dec1-gpio:
+    $ref: /schemas/types.yaml#/definitions/phandle-array
+    description: |
+        Decay mode setting pin DEC1.
+        Controls decay mode (supports fast, slow, mixed, and smart tune modes).
+
+  dir-gpio:
+    $ref: /schemas/types.yaml#/definitions/phandle-array
+    description: Logic level sets the direction of stepping; internal pulldown
+
+  pwren-gpio:
+    $ref: /schemas/types.yaml#/definitions/phandle-array
+    description: |
+        Enable driver output.
+        Logic low to enable device outputs and internal indexer; logic high to
+        disable; internal pulldown.
+
+  rampup-pwm-period-ns:
+    description: PWM period in nanoseconds during ramp-up phase
+
+  rampup-duration-ms:
+    description: Duration of ramp-up phase in milliseconds
+
+  high-pwm-period-ns:
+    description: PWM period in nanoseconds during full-speed phase
+
+  high-duration-ms:
+    description: Duration of full-speed phase in milliseconds
+
+  rampdown-pwm-period-ns:
+    description: PWM period in nanoseconds during ramp-down phase
+
+  rampdown-duration-ms:
+    description: Duration of ramp-down phase in milliseconds
+
+  step-mode:
+    $ref: /schemas/types.yaml#/definitions/uint32
+    enum: [0, 1, 2, 3, 4, 5]
+    description: |
+      Microstepping mode selection.
+        0 = Full step
+        1 = Half step
+        2 = 1/4 step
+        3 = 1/8 step
+        4 = 1/16 step
+        5 = 1/32 step
+
+  pinctrl-names:
+    const: default
+
+  pinctrl-0: true
+
+additionalProperties: false
+
+required:
+  - compatible
+  - pwms
+  - mode0-gpio
+  - mode1-gpio
+  - sleep-gpio
+  - dir-gpio
+  - pwren-gpio
+  - rampup-pwm-period-ns
+  - rampup-duration-ms
+  - high-pwm-period-ns
+  - high-duration-ms
+  - rampdown-pwm-period-ns
+  - rampdown-duration-ms
+  - step-mode
+
+examples:
+  - |
+    #include <dt-bindings/gpio/gpio.h>
+    drv8846 {
+        compatible = "ti,drv8846";
+        pwms = <&lpg 4 1000000>;
+        mode0-gpio = <&tlmm 91 GPIO_ACTIVE_HIGH>;
+        mode1-gpio = <&tlmm 66 GPIO_ACTIVE_HIGH>;
+        sleep-gpio = <&tlmm 88 GPIO_ACTIVE_HIGH>;
+        dir-gpio = <&tlmm 55 GPIO_ACTIVE_HIGH>;
+        pwren-gpio = <&tlmm 90 GPIO_ACTIVE_HIGH>;
+        rampup-pwm-period-ns = <625000>;
+        rampup-duration-ms = <50>;
+        high-pwm-period-ns = <52083>;
+        high-duration-ms = <720>;
+        rampdown-pwm-period-ns = <625000>;
+        rampdown-duration-ms = <50>;
+        step-mode = <2>;
+    };

arch/arm64/boot/dts/qcom/sm7150-xiaomi-davinci.dtsi

@@ -136,6 +136,27 @@
 		gpio = <&pm6150l_gpios 8 GPIO_ACTIVE_HIGH>;
 		vin-supply = <&vreg_s8c_1p35>;
 	};
+
+	drv8846 {
+		compatible = "ti,drv8846";
+		pwms = <&pm6150l_lpg 4 1000000>;
+		mode0-gpio = <&tlmm 91 GPIO_ACTIVE_HIGH>;
+		mode1-gpio = <&tlmm 66 GPIO_ACTIVE_HIGH>;
+		sleep-gpio = <&tlmm 88 GPIO_ACTIVE_HIGH>;
+		dir-gpio = <&tlmm 55 GPIO_ACTIVE_HIGH>;
+		pwren-gpio = <&tlmm 90 GPIO_ACTIVE_HIGH>;
+
+		rampup-pwm-period-ns = <625000>;
+		rampup-duration-ms = <50>;
+		high-pwm-period-ns = <52083>;
+		high-duration-ms = <720>;
+		rampdown-pwm-period-ns = <625000>;
+		rampdown-duration-ms = <50>;
+		step-mode = <2>;
+
+		pinctrl-names = "default";
+		pinctrl-0 = <&pwm_out_gpio10_default &motor_gpio_default &motor_gpio_fault>;
+	};
 };
 
 &battery {
@@ -369,6 +390,16 @@
 			  "MOTOR_STEP_CLK", /* GPIO_10 */
 			  "CAMT_VCM_2P8_EN",
 			  "NC";
+
+	pwm_out_gpio10_default: pwm_out_gpio10-state {
+		pins = "gpio10";
+		function = PMIC_GPIO_FUNC_FUNC1;
+		bias-disable;
+		power-source = <1>;
+		output-low;
+		qcom,drive-strength = <PMIC_GPIO_STRENGTH_LOW>;
+		drive-push-pull;
+	};
 };
 
 &pm6150l_lpg {
@@ -585,6 +616,34 @@
 		bias-pull-up;
 		input-enable;
 	};
+
+	motor_gpio_default: motor_gpio_default {
+		mux {
+			/* DIR, M0, M1, SLEEP, EN */
+			pins = "gpio55", "gpio91", "gpio66", "gpio88", "gpio90";
+			function = "gpio";
+		};
+
+		config {
+			/* DIR, M0, M1, SLEEP, EN */
+			pins = "gpio55", "gpio91", "gpio66", "gpio88", "gpio90";
+			bias-disable;
+			drive-strength = <PMIC_GPIO_STRENGTH_MED>; /* 2 MA */
+		};
+	};
+
+	motor_gpio_fault: motor_gpio_fault {
+		mux {
+			pins = "gpio43";
+			function = "gpio";
+		};
+
+		config {
+			pins = "gpio43";
+			bias-disable;
+			drive-strength = <PMIC_GPIO_STRENGTH_MED>; /* 2 MA */
+		};
+	};
 };
 
 &venus {

drivers/misc/Kconfig

@@ -643,6 +643,15 @@ config MCHP_LAN966X_PCI
 	    - lan966x-miim (MDIO_MSCC_MIIM)
 	    - lan966x-switch (LAN966X_SWITCH)
 
+config TI_DRV8846
+	tristate "TI step motor driver IC"
+	depends on PWM
+	help
+	  Say 'y' here to include support for the TI DRV8846 H-Bridge Stepper
+	  Motor Driver. The MISC peripheral holds the pwm and the driver
+	  provides an API to drive stepper motor. It allows to control a
+	  motorized pop-up front camera.
+
 source "drivers/misc/c2port/Kconfig"
 source "drivers/misc/eeprom/Kconfig"
 source "drivers/misc/cb710/Kconfig"

drivers/misc/Makefile

@@ -72,6 +72,7 @@ obj-$(CONFIG_MARVELL_CN10K_DPI)	+= mrvl_cn10k_dpi.o
 lan966x-pci-objs		:= lan966x_pci.o
 lan966x-pci-objs		+= lan966x_pci.dtbo.o
 obj-$(CONFIG_MCHP_LAN966X_PCI)	+= lan966x-pci.o
+obj-$(CONFIG_TI_DRV8846)	+= drv8846.o
 obj-y				+= keba/
 obj-y				+= amd-sbi/
-obj-$(CONFIG_MISC_RP1)		+= rp1/
+obj-$(CONFIG_MISC_RP1)		+= rp1/