Merge pull request #110 from siliconcompiler/move-lambda

mark as release candidate 1

Author: gadfort

lambdalib/__init__.py

@@ -1,3 +1,5 @@
+from siliconcompiler import DesignSchema, ASICProject
+
 #  individual modules
 from lambdalib import auxlib
 from lambdalib import fpgalib
@@ -7,7 +9,56 @@
 from lambdalib import ramlib
 from lambdalib import veclib
 
-__version__ = "0.3.4"
+__version__ = "0.4.0-rc1"
+
+
+class LambalibTechLibrary(DesignSchema):
+    """A DesignSchema class to manage a lambda library and its associated technology libraries.
+
+    This class encapsulates a main lambda library cell and a list of technology
+    libraries, providing a mechanism to alias them within an ASIC project.
+    """
+    def __init__(self, lambdalib, techlibs):
+        """Initializes the LambalibTechLibrary instance.
+
+        Args:
+            lambdalib: The main lambda library cell.
+            techlibs (list): A list of technology library classes to be associated
+                             with the main lambda library.
+        """
+        super().__init__()
+
+        self.__cell = lambdalib
+
+        if not techlibs:
+            techlibs = []
+        self.__techlibs = techlibs
+
+    @classmethod
+    def alias(cls, project: ASICProject):
+        """Creates and registers aliases for the library and its techlibs in a project.
+
+        This method checks if the provided project is an ASICProject and if the
+        lambda library cell exists within the project's libraries. If both
+        conditions are met, it adds an alias for the main library and adds
+        each associated technology library to the project's ASIC libraries.
+
+        Args:
+            project (ASICProject): The ASIC project instance to which the aliases
+                                   and libraries will be added.
+        """
+        if not isinstance(project, ASICProject):
+            return
+
+        tech = cls()
+        if not project.has_library(tech.__cell):
+            return
+
+        project.add_alias(tech.__cell, "rtl", tech, "rtl")
+
+        for lib in tech.__techlibs:
+            project.add_asiclib(lib())
+
 
 __all__ = [
     "auxlib",