Lambdalib is a modular hardware abstraction library which decouples design from the manufacturing target. The project was inspired by the Lambda concept invented during the 1978 VLSI revolution by Mead and Conway.
The original single value Lambda approach no longer applies to modern CMOS manufacturing, so Lambdalib has raised the abstraction level to the cell/block level to enable automated porting between compilation targets.
Lambdalib abstracts away technology specific design modules that cannot be cleanly expressed in technology agnostic RTL Verilog code (eg. synchronizers, analog circuits, io cells, etc.)
The table below summarizes the categories of cells available.
| Category | Description |
|---|---|
| stdlib | Standard cells (inv, nand, ff, ...) |
| auxlib | Special cells (antenna, decap, clkmux,...) |
| ramlib | Memory (single port, dual port, fifo, ...) |
| iolib | IO cells (bidir, vdd, clamp,...) |
| padring | Padring generator |
| veclib | Vectorized datapath cells (mux, buf,..) |
| fpgalib | FPGA cells (lut4, ble, clb) |
The Lambdapdk repository demonstrates implementation of the Lambdalib interfaces across a number of open source process technologies.
Lambdalib has been successfully used in multiple tapeouts using SiliconCompiler.
git clone https://github.com/zeroasiccorp/lambdalib
cd lambdalib
pip install --upgrade pip
pip install -e .This example shows how to instantiate the Padring module in a top level chip design. We could have chosen any module to instantiate (inverter, flip flop, dual port ram...).
To convert the design into a gate level netlist using yosys, just run python script
in the examples folder. A file chip.vg will be written to disk in the run directory.
$ python examples/padring/make.py- One verilog module per RTL file
- One Python module per reusable module
- Class names are RTL module names with "la_" removed and capitalized
We use GitHub Issues for tracking requests and bugs.