Merge pull request #70 from siliconcompiler/padring-lib

add clamp and add additional helper signals to poc

Author: gadfort

lambdalib/iolib/rtl/la_ioclamp.v

@@ -15,6 +15,7 @@ module la_ioclamp
     parameter RINGW = 8         // width of io ring
     )
    (// io pad signals
+    inout             pad,    // clamp supply
     inout             vdd,   // core supply
     inout             vss,   // core ground
     inout             vddio, // io supply

lambdalib/iolib/rtl/la_iopoc.v

@@ -12,14 +12,16 @@ module la_iopoc
   #(
     parameter PROP = "DEFAULT", // cell property
     parameter SIDE = "NO",      // "NO", "SO", "EA", "WE"
+    parameter CFGW = 16,        // width of core config bus
     parameter RINGW = 8         // width of io ring
     )
    (
     inout             vdd,   // core supply
     inout             vss,   // core ground
     inout             vddio, // io supply
     inout             vssio, // io ground
-    inout [RINGW-1:0] ioring // generic ioring interface
+    inout [RINGW-1:0] ioring,// generic ioring interface
+    input [CFGW-1:0]  cfg    // generic config interface
     );
 
 endmodule

lambdalib/padring/rtl/la_iopadring.vh

@@ -25,3 +25,4 @@ localparam [7:0] LA_VDDA   = 8'h14;
 localparam [7:0] LA_VSSA   = 8'h15;
 localparam [7:0] LA_POC    = 8'h16;
 localparam [7:0] LA_CUT    = 8'h17;
+localparam [7:0] LA_CLAMP  = 8'h18;

lambdalib/padring/rtl/la_ioside.v

@@ -195,8 +195,10 @@ module la_ioside
           begin : gpoc
              la_iopoc #(.SIDE(SIDE),
                         .PROP(CELLMAP[(i*40+32)+:8]),
+                        .CFGW(CFGW),
                         .RINGW(RINGW))
-             i0 (.vss(vss),
+             i0 (.cfg(cfg[CELLMAP[(i*40)+:8]*CFGW+:CFGW]),
+                 .vss(vss),
                  .vdd(vdd[CELLMAP[(i*40+24)+:8]]),
                  .vddio(vddio[CELLMAP[(i*40+24)+:8]]),
                  .vssio(vssio[CELLMAP[(i*40+24)+:8]]),
@@ -210,6 +212,7 @@ module la_ioside
                         .RINGW(RINGW))
              i0 (.vss(vss));
           end
+        // LA_VDDIO
         if (CELLMAP[(i*40+16)+:8] == LA_VDDIO)
           begin : gvddio
              la_iovddio #(.SIDE(SIDE),
@@ -282,6 +285,19 @@ module la_ioside
                  .vssio(vssio[CELLMAP[(i*40+24)+:8]]),
                  .ioring(ioring[CELLMAP[(i*40+24)+:8]*RINGW+:RINGW]));
           end
+        // LA_CLAMP
+        if (CELLMAP[(i*40+16)+:8] == LA_CLAMP)
+          begin : gclamp
+            la_iovssa #(.SIDE(SIDE),
+                        .PROP(CELLMAP[(i*40+32)+:8]),
+                        .RINGW(RINGW))
+             i0 (.pad(pad[CELLMAP[(i*40)+:8]]),
+                 .vss(vss),
+                 .vdd(vdd[CELLMAP[(i*40+24)+:8]]),
+                 .vddio(vddio[CELLMAP[(i*40+24)+:8]]),
+                 .vssio(vssio[CELLMAP[(i*40+24)+:8]]),
+                 .ioring(ioring[CELLMAP[(i*40+24)+:8]*RINGW+:RINGW]));
+          end
      end
 
 endmodule