Split rams into impl and wrappers

azaidy · azaidy · commit c0c6c854ecd4 · 2024-11-06T10:51:40.000-05:00
diff --git a/lambdalib/ramlib/rtl/la_dpram.v b/lambdalib/ramlib/rtl/la_dpram.v
@@ -47,16 +47,31 @@ module la_dpram #(
     input [TESTW-1:0] test  // pass through ASIC test interface
 );
 
-    // Generic RTL RAM
-    reg     [DW-1:0] ram[(2**AW)-1:0];
-    integer          i;
+    la_dpram_impl #(
+        .DW         (DW),
+        .AW         (AW),
+        .PROP       (PROP),
+        .CTRLW      (CTRLW),
+        .TESTW      (TESTW)
+    ) ram (
+        .wr_clk     (wr_clk),
+        .wr_ce      (wr_ce),
+        .wr_we      (wr_we),
+        .wr_wmask   (wr_wmask),
+        .wr_addr    (wr_addr),
+        .wr_din     (wr_din),
 
-    // Write port
-    always @(posedge wr_clk)
-        for (i = 0; i < DW; i = i + 1)
-            if (wr_ce & wr_we & wr_wmask[i]) ram[wr_addr[AW-1:0]][i] <= wr_din[i];
+        .rd_clk     (rd_clk),
+        .rd_ce      (rd_ce),
+        .rd_addr    (rd_addr),
+        .rd_dout    (rd_dout),
 
-    // Read Port
-    always @(posedge rd_clk) if (rd_ce) rd_dout[DW-1:0] <= ram[rd_addr[AW-1:0]];
+        .vss        (vss),
+        .vdd        (vdd),
+        .vddio      (vddio),
+
+        .ctrl       (ctrl),
+        .test       (test)
+    );
 
 endmodule
diff --git a/lambdalib/ramlib/rtl/la_dpram_impl.v b/lambdalib/ramlib/rtl/la_dpram_impl.v
@@ -0,0 +1,62 @@
+/*****************************************************************************
+ * Function: Dual Port RAM (One write port + One read port)
+ * Copyright: Lambda Project Authors. All rights Reserved.
+ * License:  MIT (see LICENSE file in Lambda repository)
+ *
+ * Docs:
+ *
+ * This is a wrapper for selecting from a set of hardened memory macros.
+ *
+ * A synthesizable reference model is used when the PROP is DEFAULT. The
+ * synthesizable model does not implement the cfg and test interface and should
+ * only be used for basic testing and for synthesizing for FPGA devices.
+ * Advanced ASIC development should rely on complete functional models
+ * supplied on a per macro basis.
+ *
+ * Technologoy specific implementations of "la_dpram" would generally include
+ * one or more hardcoded instantiations of RAM modules with a generate
+ * statement relying on the "PROP" to select between the list of modules
+ * at build time.
+ *
+ ****************************************************************************/
+
+module la_dpram_impl #(
+    parameter DW    = 32,         // Memory width
+    parameter AW    = 10,         // address width (derived)
+    parameter PROP  = "DEFAULT",  // pass through variable for hard macro
+    parameter CTRLW = 128,        // width of asic ctrl interface
+    parameter TESTW = 128         // width of asic test interface
+) (  // Write port
+    input wr_clk,  // write clock
+    input wr_ce,  // write chip-enable
+    input wr_we,  // write enable
+    input [DW-1:0] wr_wmask,  // write mask
+    input [AW-1:0] wr_addr,  // write address
+    input [DW-1:0] wr_din,  //write data in
+    // Read port
+    input rd_clk,  // read clock
+    input rd_ce,  // read chip-enable
+    input [AW-1:0] rd_addr,  // read address
+    output reg [DW-1:0] rd_dout,  //read data out
+    // Power signal
+    input vss,  // ground signal
+    input vdd,  // memory core array power
+    input vddio,  // periphery/io power
+    // Generic interfaces
+    input [CTRLW-1:0] ctrl,  // pass through ASIC control interface
+    input [TESTW-1:0] test  // pass through ASIC test interface
+);
+
+    // Generic RTL RAM
+    reg     [DW-1:0] ram[(2**AW)-1:0];
+    integer          i;
+
+    // Write port
+    always @(posedge wr_clk)
+        for (i = 0; i < DW; i = i + 1)
+            if (wr_ce & wr_we & wr_wmask[i]) ram[wr_addr[AW-1:0]][i] <= wr_din[i];
+
+    // Read Port
+    always @(posedge rd_clk) if (rd_ce) rd_dout[DW-1:0] <= ram[rd_addr[AW-1:0]];
+
+endmodule
diff --git a/lambdalib/ramlib/rtl/la_spram.v b/lambdalib/ramlib/rtl/la_spram.v
@@ -43,22 +43,27 @@ module la_spram #(
     input [TESTW-1:0] test  // pass through ASIC test interface
 );
 
-    // Generic RTL RAM
-    reg     [DW-1:0] ram[(2**AW)-1:0];
-    integer          i;
+    la_spram_impl #(
+        .DW     (DW),
+        .AW     (AW),
+        .PROP   (PROP),
+        .CTRLW  (CTRLW),
+        .TESTW  (TESTW),
+    ) ram (
+        .clk    (clk),
+        .ce     (ce),
+        .we     (we),
+        .wmask  (wmask),
+        .addr   (addr),
+        .din    (din),
+        .dout   (dout),
 
-    // Write port
-    //   always @(posedge clk)
-    //     for (i=0;i<DW;i=i+1)
-    //       if (ce & we & wmask[i])
-    //         ram[addr[AW-1:0]][i] <= din[i];
+        .vss    (vss),
+        .vdd    (vdd),
+        .vddio  (vddio),
 
-    // Re-writing as a mux for verilator
-    always @(posedge clk)
-        if (ce & we)
-            ram[addr[AW-1:0]] <= din[DW-1:0] & wmask[DW-1:0] | ram[addr[AW-1:0]] & ~wmask[DW-1:0];
-
-    // Read Port
-    always @(posedge clk) if (ce) dout[DW-1:0] <= ram[addr[AW-1:0]];
+        .ctrl   (ctrl),
+        .test   (test)
+    );
 
 endmodule
diff --git a/lambdalib/ramlib/rtl/la_spram_impl.v b/lambdalib/ramlib/rtl/la_spram_impl.v
@@ -0,0 +1,64 @@
+/*****************************************************************************
+ * Function: Single Port RAM
+ * Copyright: Lambda Project Authors. All rights Reserved.
+ * License:  MIT (see LICENSE file in Lambda repository)
+ *
+ * Docs:
+ *
+ * This is a wrapper for selecting from a set of hardened memory macros.
+ *
+ * A synthesizable reference model is used when the PROP is DEFAULT. The
+ * synthesizable model does not implement the cfg and test interface and should
+ * only be used for basic testing and for synthesizing for FPGA devices.
+ * Advanced ASIC development should rely on complete functional models
+ * supplied on a per macro basis.
+ *
+ * Technologoy specific implementations of "la_spram" would generally include
+ * one or more hardcoded instantiations of RAM modules with a generate
+ * statement relying on the "PROP" to select between the list of modules
+ * at build time.
+ *
+ ****************************************************************************/
+
+module la_spram_impl #(
+    parameter DW    = 32,         // Memory width
+    parameter AW    = 10,         // Address width (derived)
+    parameter PROP  = "DEFAULT",  // Pass through variable for hard macro
+    parameter CTRLW = 1,          // Width of asic ctrl interface
+    parameter TESTW = 1           // Width of asic test interface
+) (  // Memory interface
+    input clk,  // write clock
+    input ce,  // chip enable
+    input we,  // write enable
+    input [DW-1:0] wmask,  //per bit write mask
+    input [AW-1:0] addr,  //write address
+    input [DW-1:0] din,  //write data
+    output reg [DW-1:0] dout,  //read output data
+    // Power signals
+    input vss,  // ground signal
+    input vdd,  // memory core array power
+    input vddio,  // periphery/io power
+    // Generic interfaces
+    input [CTRLW-1:0] ctrl,  // pass through ASIC control interface
+    input [TESTW-1:0] test  // pass through ASIC test interface
+);
+
+    // Generic RTL RAM
+    reg     [DW-1:0] ram[(2**AW)-1:0];
+    integer          i;
+
+    // Write port
+    //   always @(posedge clk)
+    //     for (i=0;i<DW;i=i+1)
+    //       if (ce & we & wmask[i])
+    //         ram[addr[AW-1:0]][i] <= din[i];
+
+    // Re-writing as a mux for verilator
+    always @(posedge clk)
+        if (ce & we)
+            ram[addr[AW-1:0]] <= din[DW-1:0] & wmask[DW-1:0] | ram[addr[AW-1:0]] & ~wmask[DW-1:0];
+
+    // Read Port
+    always @(posedge clk) if (ce) dout[DW-1:0] <= ram[addr[AW-1:0]];
+
+endmodule
