Merge pull request #67 from siliconcompiler/sc-update

gadfort · web-flow · commit c0aae8d533d5 · 2024-07-30T15:31:58.000-04:00
split into separate importable modules
diff --git a/README.md b/README.md
@@ -1,6 +1,6 @@
 # Lambdalib Introduction
 
-Lambdalib is a modular hardware abstraction library decouples design from the uderlying manufacturing target. Lambdalib defines a set of generic functions that get resolved during the target technology mapping stage.
+Lambdalib is a modular hardware abstraction library decouples design from the underlying manufacturing target. Lambdalib defines a set of generic functions that get resolved during the target technology mapping stage.
 
 Lambdalib includes the following hardware categories:
 
diff --git a/lambdalib/__init__.py b/lambdalib/__init__.py
@@ -1,60 +1,47 @@
-from siliconcompiler import Chip, Library
+from siliconcompiler import Chip
 import siliconcompiler.package as sc_package
 import glob
 import os
 import shutil
 
-__version__ = "0.2.7"
+from lambdalib import _common
+from lambdalib import \
+    auxlib, \
+    fpgalib, \
+    iolib, \
+    padring, \
+    ramlib, \
+    stdlib, \
+    syslib, \
+    vectorlib
 
-_libraries = (
-    'iolib',
-    'stdlib',
-    'auxlib',
-    'ramlib',
-    'padring',
-    'syslib',
-    'vectorlib',
-    'fpgalib'
-)
+
+__version__ = _common._version
 
 
 ########################
 # SiliconCompiler Setup
 ########################
 def setup(chip):
-    '''Lambdalib library setup script'''
-
-    add_idirs = ('padring',)
-
-    libs = []
-    # Iterate over all libs
-    for name in _libraries:
-        lib = Library(chip, f'lambdalib_{name}', package='lambdalib')
-        register_data_source(lib)
-
-        lib.add('option', 'ydir', f"lambdalib/{name}/rtl")
-
-        if name in add_idirs:
-            lib.add('option', 'idir', f"lambdalib/{name}/rtl")
-
-        libs.append(lib)
-
-    return libs
-
-
-def register_data_source(chip):
-    sc_package.register_python_data_source(
-        chip,
-        "lambdalib",
-        "lambdalib",
-        "git+https://github.com/siliconcompiler/lambdalib.git",
-        alternative_ref=f"v{__version__}",
-        python_module_path_append="..")
+    '''
+    Lambdalib library setup script
+    '''
+
+    return [
+        auxlib.setup(chip),
+        fpgalib.setup(chip),
+        iolib.setup(chip),
+        padring.setup(chip),
+        ramlib.setup(chip),
+        stdlib.setup(chip),
+        syslib.setup(chip),
+        vectorlib.setup(chip)
+    ]
 
 
 def __get_lambdalib_dir(la_lib):
     path_assert = Chip('lambdalib')
-    register_data_source(path_assert)
+    _common.register_data_source(path_assert)
     lambdalib_path = sc_package.path(path_assert, 'lambdalib')
     return f'{lambdalib_path}/lambdalib/{la_lib}/rtl'
 
diff --git a/lambdalib/_common.py b/lambdalib/_common.py
@@ -0,0 +1,14 @@
+import siliconcompiler.package as sc_package
+
+
+_version = "0.2.8"
+
+
+def register_data_source(chip):
+    sc_package.register_python_data_source(
+        chip,
+        "lambdalib",
+        "lambdalib",
+        "git+https://github.com/siliconcompiler/lambdalib.git",
+        alternative_ref=f"v{_version}",
+        python_module_path_append="..")
diff --git a/lambdalib/auxlib/__init__.py b/lambdalib/auxlib/__init__.py
@@ -0,0 +1,21 @@
+from siliconcompiler import Library
+from lambdalib._common import register_data_source
+from lambdalib import stdlib
+
+
+########################
+# SiliconCompiler Setup
+########################
+def setup(chip):
+    '''
+    Lambdalib auxlib
+    '''
+
+    lib = Library(chip, 'lambdalib_auxlib', package='lambdalib', auto_enable=True)
+    register_data_source(lib)
+
+    lib.add('option', 'ydir', "lambdalib/auxlib/rtl")
+
+    lib.use(stdlib)
+
+    return lib
diff --git a/lambdalib/auxlib/rtl/la_oddr.v b/lambdalib/auxlib/rtl/la_oddr.v
@@ -17,7 +17,7 @@ module la_oddr #(
     reg in1_sh;
     always @(clk or in1) if (~clk) in1_sh <= in1;
 
-    //Using clock as data selctor
+    //Using clock as data selector
     assign out = clk ? in1_sh : in0;
 
 endmodule
diff --git a/lambdalib/fpgalib/__init__.py b/lambdalib/fpgalib/__init__.py
@@ -0,0 +1,18 @@
+from siliconcompiler import Library
+from lambdalib._common import register_data_source
+
+
+########################
+# SiliconCompiler Setup
+########################
+def setup(chip):
+    '''
+    Lambdalib fpgalib
+    '''
+
+    lib = Library(chip, 'lambdalib_fpgalib', package='lambdalib', auto_enable=True)
+    register_data_source(lib)
+
+    lib.add('option', 'ydir', "lambdalib/fpgalib/rtl")
+
+    return lib
diff --git a/lambdalib/fpgalib/rtl/la_clb4p0.v b/lambdalib/fpgalib/rtl/la_clb4p0.v
@@ -25,7 +25,7 @@
  *
  * 1. N=2, I=4
  * 2. test1: CLB configured as separate and4, or4 gates
- * 3. test2" LB confiugred as combined and7 (in[7]=ignored)
+ * 3. test2" LB configured as combined and7 (in[7]=ignored)
  *
  ******************************************************************************/
 
diff --git a/lambdalib/iolib/README.md b/lambdalib/iolib/README.md
@@ -6,7 +6,7 @@
 | ---------------------------------|---------|-----------------------------|
 [[la_iobidir](./rtl/la_iobidir.v)  | Digital | Bidirectional
 [la_ioinput](./rtl/la_ioinput.v)   | Digital | Input
-[la_ioxtal](./rtl/la_ioxtal.v)     | Digital | Xtal tranceiver
+[la_ioxtal](./rtl/la_ioxtal.v)     | Digital | Xtal transceiver
 [la_iorxdiff](./rtl/la_iorxdiff.v) | Digital | Differential input
 [la_iotxdiff](./rtl/la_iotxdiff.v) | Digital | Differential output
 [la_ioanalog](./rtl/la_ioanalog.v) | Analog  | Pass through ESD protection
@@ -24,7 +24,7 @@
 ## PARAMETERS
 
 ### CFGW
-The `CFGW` parameter defines the width of the configuration bus of the io cell. IO cells generally include a set of configuration inputs for things like drive strength and operating modes. Setting `CFGW` to a large value (eg. 16/32) should have zero impact on the design as the extra bus bits get optimized away during implementation. The connection between the generic `CFG` bus and the technology specific IO cell is done within the techology specific cell wrapper library.
+The `CFGW` parameter defines the width of the configuration bus of the io cell. IO cells generally include a set of configuration inputs for things like drive strength and operating modes. Setting `CFGW` to a large value (eg. 16/32) should have zero impact on the design as the extra bus bits get optimized away during implementation. The connection between the generic `CFG` bus and the technology specific IO cell is done within the technology specific cell wrapper library.
 
 For la_bidir, the first 8 bits of the configuration bus are reserved for the functionality shown in the table below.
 
diff --git a/lambdalib/iolib/__init__.py b/lambdalib/iolib/__init__.py
@@ -0,0 +1,18 @@
+from siliconcompiler import Library
+from lambdalib._common import register_data_source
+
+
+########################
+# SiliconCompiler Setup
+########################
+def setup(chip):
+    '''
+    Lambdalib iolib
+    '''
+
+    lib = Library(chip, 'lambdalib_iolib', package='lambdalib', auto_enable=True)
+    register_data_source(lib)
+
+    lib.add('option', 'ydir', "lambdalib/iolib/rtl")
+
+    return lib
diff --git a/lambdalib/padring/README.md b/lambdalib/padring/README.md
@@ -7,7 +7,7 @@ The lamdbdalib `padring` library is an automated "pure verilog" padring generato
 ## PARAMETERS
 
 ### {NO,EA,WE,SO}NCELLS
-Specifies the total number of placed cells within one side of the padring, includig supply and clamp cells.
+Specifies the total number of placed cells within one side of the padring, including supply and clamp cells.
 
 ### {NO,EA,WE,SO}NPINS
 Specifies the total number of logical device pins (pads) connected to one side of the padring, not including supply pins. The `CELLMAP` parameter specifies which one of the pins should be connected to a cell.
diff --git a/lambdalib/padring/__init__.py b/lambdalib/padring/__init__.py
@@ -0,0 +1,22 @@
+from siliconcompiler import Library
+from lambdalib._common import register_data_source
+from lambdalib import iolib
+
+
+########################
+# SiliconCompiler Setup
+########################
+def setup(chip):
+    '''
+    Lambdalib padring
+    '''
+
+    lib = Library(chip, 'lambdalib_padring', package='lambdalib', auto_enable=True)
+    register_data_source(lib)
+
+    lib.add('option', 'idir', "lambdalib/padring/rtl")
+    lib.add('option', 'ydir', "lambdalib/padring/rtl")
+
+    lib.use(iolib)
+
+    return lib
diff --git a/lambdalib/ramlib/__init__.py b/lambdalib/ramlib/__init__.py
@@ -0,0 +1,21 @@
+from siliconcompiler import Library
+from lambdalib._common import register_data_source
+from lambdalib import auxlib
+
+
+########################
+# SiliconCompiler Setup
+########################
+def setup(chip):
+    '''
+    Lambdalib ramlib
+    '''
+
+    lib = Library(chip, 'lambdalib_ramlib', package='lambdalib', auto_enable=True)
+    register_data_source(lib)
+
+    lib.add('option', 'ydir', "lambdalib/ramlib/rtl")
+
+    lib.use(auxlib)
+
+    return lib
diff --git a/lambdalib/ramlib/rtl/la_asyncfifo.v b/lambdalib/ramlib/rtl/la_asyncfifo.v
@@ -14,7 +14,7 @@
  * supplied on a per macro basis.
  *
  * Technologoy specific implementations of "la_dpram" would generally include
- * one ore more hardcoded instantiations of RAM modules with a generate
+ * one or more hardcoded instantiations of RAM modules with a generate
  * statement relying on the "PROP" to select between the list of modules
  * at build time.
  *
diff --git a/lambdalib/ramlib/rtl/la_dpram.v b/lambdalib/ramlib/rtl/la_dpram.v
@@ -14,7 +14,7 @@
  * supplied on a per macro basis.
  *
  * Technologoy specific implementations of "la_dpram" would generally include
- * one ore more hardcoded instantiations of RAM modules with a generate
+ * one or more hardcoded instantiations of RAM modules with a generate
  * statement relying on the "PROP" to select between the list of modules
  * at build time.
  *
diff --git a/lambdalib/ramlib/rtl/la_spram.v b/lambdalib/ramlib/rtl/la_spram.v
@@ -14,7 +14,7 @@
  * supplied on a per macro basis.
  *
  * Technologoy specific implementations of "la_spram" would generally include
- * one ore more hardcoded instantiations of RAM modules with a generate
+ * one or more hardcoded instantiations of RAM modules with a generate
  * statement relying on the "PROP" to select between the list of modules
  * at build time.
  *
diff --git a/lambdalib/ramlib/rtl/la_spregfile.v b/lambdalib/ramlib/rtl/la_spregfile.v
@@ -14,7 +14,7 @@
  * supplied on a per macro basis.
  *
  * Technologoy specific implementations of "la_spregfile" would generally
- * include one ore more hardcoded instantiations of RF modules with a generate
+ * include one or more hardcoded instantiations of RF modules with a generate
  * statement relying on the "PROP" to select between the list of modules
  * at build time.
  *
diff --git a/lambdalib/stdlib/__init__.py b/lambdalib/stdlib/__init__.py
@@ -0,0 +1,18 @@
+from siliconcompiler import Library
+from lambdalib._common import register_data_source
+
+
+########################
+# SiliconCompiler Setup
+########################
+def setup(chip):
+    '''
+    Lambdalib stdlib
+    '''
+
+    lib = Library(chip, 'lambdalib_stdlib', package='lambdalib', auto_enable=True)
+    register_data_source(lib)
+
+    lib.add('option', 'ydir', "lambdalib/stdlib/rtl")
+
+    return lib
diff --git a/lambdalib/syslib/__init__.py b/lambdalib/syslib/__init__.py
@@ -0,0 +1,18 @@
+from siliconcompiler import Library
+from lambdalib._common import register_data_source
+
+
+########################
+# SiliconCompiler Setup
+########################
+def setup(chip):
+    '''
+    Lambdalib syslib
+    '''
+
+    lib = Library(chip, 'lambdalib_syslib', package='lambdalib', auto_enable=True)
+    register_data_source(lib)
+
+    lib.add('option', 'ydir', "lambdalib/syslib/rtl")
+
+    return lib
diff --git a/lambdalib/utils/templates/la_spmemory.v b/lambdalib/utils/templates/la_spmemory.v
@@ -14,7 +14,7 @@
  * supplied on a per macro basis.
  *
  * Technologoy specific implementations of "la_sp{{ type }}" would generally include
- * one ore more hardcoded instantiations of {{ type }} modules with a generate
+ * one or more hardcoded instantiations of {{ type }} modules with a generate
  * statement relying on the "PROP" to select between the list of modules
  * at build time.
  *
diff --git a/lambdalib/vectorlib/__init__.py b/lambdalib/vectorlib/__init__.py
@@ -0,0 +1,21 @@
+from siliconcompiler import Library
+from lambdalib._common import register_data_source
+from lambdalib import stdlib
+
+
+########################
+# SiliconCompiler Setup
+########################
+def setup(chip):
+    '''
+    Lambdalib vectorlib
+    '''
+
+    lib = Library(chip, 'lambdalib_vectorlib', package='lambdalib', auto_enable=True)
+    register_data_source(lib)
+
+    lib.add('option', 'ydir', "lambdalib/vectorlib/rtl")
+
+    lib.use(stdlib)
+
+    return lib
diff --git a/pyproject.toml b/pyproject.toml
@@ -20,13 +20,13 @@ urls = {Homepage = "https://github.com/siliconcompiler/lambdalib"}
 requires-python = ">= 3.8"
 license = {file = "LICENSE"}
 dependencies = [
-    "siliconcompiler >= 0.20.2",
+    "siliconcompiler >= 0.26.0",
     "Jinja2 >= 3.1.3"
 ]
 dynamic = ['version']
 
 [tool.setuptools.dynamic]
-version = {attr = "lambdalib.__version__"}
+version = {attr = "lambdalib._common._version"}
 
 [tool.pytest.ini_options]
 testpaths = "tests"
diff --git a/tests/test_local_detect.py b/tests/test_local_detect.py
@@ -1,5 +1,5 @@
 from siliconcompiler import Chip
-from lambdalib import register_data_source
+from lambdalib._common import register_data_source
 
 
 def test_local_install_detection():
diff --git a/tests/test_setup.py b/tests/test_setup.py

Original file line number	Diff line number	Diff line change
`@@ -25,7 +25,7 @@`
`25`	`25`	`*`
`26`	`26`	`* 1. N=2, I=4`
`27`	`27`	`* 2. test1: CLB configured as separate and4, or4 gates`
`28`		`- * 3. test2" LB confiugred as combined and7 (in[7]=ignored)`
	`28`	`+ * 3. test2" LB configured as combined and7 (in[7]=ignored)`
`29`	`29`	`*`
`30`	`30`	`******************************************************************************/`
`31`	`31`