Restructuring of files

ArriaVADCEthernet_top.qsf

@@ -243,11 +243,6 @@ set_instance_assignment -name IO_MAXIMUM_TOGGLE_RATE "10 MHz" -to fm_d[14]
 set_instance_assignment -name IO_MAXIMUM_TOGGLE_RATE "10 MHz" -to fm_d[15]
 set_instance_assignment -name GLOBAL_SIGNAL GLOBAL_CLOCK -to clkin_50
 set_instance_assignment -name GLOBAL_SIGNAL GLOBAL_CLOCK -to enet_rx_clk
-set_global_assignment -name QIP_FILE adc_pll.qip
-set_global_assignment -name SDC_FILE ArriaVADCEthernet_top.sdc
-set_global_assignment -name QIP_FILE a5gx_starter_fpga_bup_qsys/synthesis/a5gx_starter_fpga_bup_qsys.qip
-set_global_assignment -name QIP_FILE enet_gtx_clk_ddio_buffer.qip
-set_global_assignment -name CDF_FILE ArriaVADCEthernet_top.cdf
 set_location_assignment PIN_AH13 -to ad_sclk
 set_location_assignment PIN_AD6 -to ad_sdio
 set_location_assignment PIN_C1 -to ada_dco
@@ -290,15 +285,8 @@ set_location_assignment PIN_AC8 -to fpga_clk_a_n
 set_location_assignment PIN_AD8 -to fpga_clk_a_p
 set_location_assignment PIN_M8 -to fpga_clk_b_n
 set_location_assignment PIN_L9 -to fpga_clk_b_p
-set_global_assignment -name SYSTEMVERILOG_FILE ArriaVADCEthernet_top.sv
-set_global_assignment -name SYSTEMVERILOG_FILE delayVec.sv
-set_global_assignment -name SYSTEMVERILOG_FILE waveformGenerator.sv
-set_global_assignment -name VERILOG_FILE trigger.v
 set_global_assignment -name ENABLE_SIGNALTAP ON
 set_global_assignment -name USE_SIGNALTAP_FILE ArriaVADCEthernet_top.stp
-set_global_assignment -name SIGNALTAP_FILE ArriaVADCEthernet_top.stp
-set_global_assignment -name SYSTEMVERILOG_FILE getSample.sv
-set_global_assignment -name QIP_FILE ADC_Mux.qip
 set_global_assignment -name SLD_NODE_CREATOR_ID 110 -section_id nios
 set_global_assignment -name SLD_NODE_ENTITY_NAME sld_signaltap -section_id nios
 set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_RAM_BLOCK_TYPE=AUTO" -section_id nios
@@ -357,7 +345,6 @@ set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_COUNTER_PIPELINE=
 set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_ADVANCED_TRIGGER_ENTITY=basic,1," -section_id adc
 set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_TRIGGER_LEVEL_PIPELINE=1" -section_id adc
 set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_ENABLE_ADVANCED_TRIGGER=0" -section_id adc
-set_global_assignment -name VERILOG_FILE adcSync.v
 set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[0] -to "adcSync:sync_a|ADCin[0]" -section_id adc
 set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[1] -to "adcSync:sync_a|ADCin[10]" -section_id adc
 set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[2] -to "adcSync:sync_a|ADCin[11]" -section_id adc
@@ -1858,5 +1845,18 @@ set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[28] -
 set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[31] -to nios|vcc -section_id nios
 set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_ADVANCED_TRIGGER_ENTITY=basic,1,sld_reserved_ArriaVADCEthernet_nios_2_e991," -section_id nios
 set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_clk -to "adc_pll:adc_pll|outclk_0" -section_id nios
+set_global_assignment -name SYSTEMVERILOG_FILE ArriaVADCEthernet_top.sv
+set_global_assignment -name SDC_FILE ArriaVADCEthernet_top.sdc
+set_global_assignment -name CDF_FILE ArriaVADCEthernet_top.cdf
+set_global_assignment -name SIGNALTAP_FILE ArriaVADCEthernet_top.stp
+set_global_assignment -name QIP_FILE adc_mux/ADC_Mux.qip
+set_global_assignment -name QIP_FILE ddio_buffer/enet_gtx_clk_ddio_buffer.qip
+set_global_assignment -name QIP_FILE a5gx_starter_fpga_bup_qsys/synthesis/a5gx_starter_fpga_bup_qsys.qip
+set_global_assignment -name QIP_FILE adc_pll/adc_pll.qip
+set_global_assignment -name VERILOG_FILE src/trigger.v
+set_global_assignment -name VERILOG_FILE src/adcSync.v
+set_global_assignment -name SYSTEMVERILOG_FILE src/delayVec.sv
+set_global_assignment -name SYSTEMVERILOG_FILE src/waveformGenerator.sv
+set_global_assignment -name SYSTEMVERILOG_FILE src/getSample.sv
 set_global_assignment -name SLD_FILE db/ArriaVADCEthernet_top_auto_stripped.stp
 set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

adc_mux/ADC_Mux.qip

@@ -0,0 +1,6 @@
+set_global_assignment -name IP_TOOL_NAME "LPM_MUX"
+set_global_assignment -name IP_TOOL_VERSION "16.1"
+set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Arria V}"
+set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "ADC_Mux.v"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "ADC_Mux_inst.v"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "ADC_Mux_bb.v"]

adc_mux/ADC_Mux.v

@@ -0,0 +1,104 @@
+// megafunction wizard: %LPM_MUX%
+// GENERATION: STANDARD
+// VERSION: WM1.0
+// MODULE: LPM_MUX 
+
+// ============================================================
+// File Name: ADC_Mux.v
+// Megafunction Name(s):
+// 			LPM_MUX
+//
+// Simulation Library Files(s):
+// 			lpm
+// ============================================================
+// ************************************************************
+// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+//
+// 16.1.0 Build 196 10/24/2016 SJ Standard Edition
+// ************************************************************
+
+
+//Copyright (C) 2016  Intel Corporation. All rights reserved.
+//Your use of Intel Corporation's design tools, logic functions 
+//and other software and tools, and its AMPP partner logic 
+//functions, and any output files from any of the foregoing 
+//(including device programming or simulation files), and any 
+//associated documentation or information are expressly subject 
+//to the terms and conditions of the Intel Program License 
+//Subscription Agreement, the Intel Quartus Prime License Agreement,
+//the Intel MegaCore Function License Agreement, or other 
+//applicable license agreement, including, without limitation, 
+//that your use is for the sole purpose of programming logic 
+//devices manufactured by Intel and sold by Intel or its 
+//authorized distributors.  Please refer to the applicable 
+//agreement for further details.
+
+
+// synopsys translate_off
+`timescale 1 ps / 1 ps
+// synopsys translate_on
+module ADC_Mux (
+	data0x,
+	data1x,
+	sel,
+	result);
+
+	input	[13:0]  data0x;
+	input	[13:0]  data1x;
+	input	  sel;
+	output	[13:0]  result;
+
+	wire [13:0] sub_wire0;
+	wire [13:0] sub_wire3 = data1x[13:0];
+	wire [13:0] result = sub_wire0[13:0];
+	wire [13:0] sub_wire1 = data0x[13:0];
+	wire [27:0] sub_wire2 = {sub_wire3, sub_wire1};
+	wire  sub_wire4 = sel;
+	wire  sub_wire5 = sub_wire4;
+
+	lpm_mux	LPM_MUX_component (
+				.data (sub_wire2),
+				.sel (sub_wire5),
+				.result (sub_wire0)
+				// synopsys translate_off
+				,
+				.aclr (),
+				.clken (),
+				.clock ()
+				// synopsys translate_on
+				);
+	defparam
+		LPM_MUX_component.lpm_size = 2,
+		LPM_MUX_component.lpm_type = "LPM_MUX",
+		LPM_MUX_component.lpm_width = 14,
+		LPM_MUX_component.lpm_widths = 1;
+
+
+endmodule
+
+// ============================================================
+// CNX file retrieval info
+// ============================================================
+// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Arria V"
+// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+// Retrieval info: PRIVATE: new_diagram STRING "1"
+// Retrieval info: LIBRARY: lpm lpm.lpm_components.all
+// Retrieval info: CONSTANT: LPM_SIZE NUMERIC "2"
+// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_MUX"
+// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "14"
+// Retrieval info: CONSTANT: LPM_WIDTHS NUMERIC "1"
+// Retrieval info: USED_PORT: data0x 0 0 14 0 INPUT NODEFVAL "data0x[13..0]"
+// Retrieval info: USED_PORT: data1x 0 0 14 0 INPUT NODEFVAL "data1x[13..0]"
+// Retrieval info: USED_PORT: result 0 0 14 0 OUTPUT NODEFVAL "result[13..0]"
+// Retrieval info: USED_PORT: sel 0 0 0 0 INPUT NODEFVAL "sel"
+// Retrieval info: CONNECT: @data 0 0 14 0 data0x 0 0 14 0
+// Retrieval info: CONNECT: @data 0 0 14 14 data1x 0 0 14 0
+// Retrieval info: CONNECT: @sel 0 0 1 0 sel 0 0 0 0
+// Retrieval info: CONNECT: result 0 0 14 0 @result 0 0 14 0
+// Retrieval info: GEN_FILE: TYPE_NORMAL ADC_Mux.v TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL ADC_Mux.inc FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL ADC_Mux.cmp FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL ADC_Mux.bsf FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL ADC_Mux_inst.v TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL ADC_Mux_bb.v TRUE
+// Retrieval info: LIB_FILE: lpm

adc_mux/ADC_Mux_bb.v

@@ -0,0 +1,73 @@
+// megafunction wizard: %LPM_MUX%VBB%
+// GENERATION: STANDARD
+// VERSION: WM1.0
+// MODULE: LPM_MUX 
+
+// ============================================================
+// File Name: ADC_Mux.v
+// Megafunction Name(s):
+// 			LPM_MUX
+//
+// Simulation Library Files(s):
+// 			lpm
+// ============================================================
+// ************************************************************
+// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+//
+// 16.1.0 Build 196 10/24/2016 SJ Standard Edition
+// ************************************************************
+
+//Copyright (C) 2016  Intel Corporation. All rights reserved.
+//Your use of Intel Corporation's design tools, logic functions 
+//and other software and tools, and its AMPP partner logic 
+//functions, and any output files from any of the foregoing 
+//(including device programming or simulation files), and any 
+//associated documentation or information are expressly subject 
+//to the terms and conditions of the Intel Program License 
+//Subscription Agreement, the Intel Quartus Prime License Agreement,
+//the Intel MegaCore Function License Agreement, or other 
+//applicable license agreement, including, without limitation, 
+//that your use is for the sole purpose of programming logic 
+//devices manufactured by Intel and sold by Intel or its 
+//authorized distributors.  Please refer to the applicable 
+//agreement for further details.
+
+module ADC_Mux (
+	data0x,
+	data1x,
+	sel,
+	result);
+
+	input	[13:0]  data0x;
+	input	[13:0]  data1x;
+	input	  sel;
+	output	[13:0]  result;
+
+endmodule
+
+// ============================================================
+// CNX file retrieval info
+// ============================================================
+// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Arria V"
+// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+// Retrieval info: PRIVATE: new_diagram STRING "1"
+// Retrieval info: LIBRARY: lpm lpm.lpm_components.all
+// Retrieval info: CONSTANT: LPM_SIZE NUMERIC "2"
+// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_MUX"
+// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "14"
+// Retrieval info: CONSTANT: LPM_WIDTHS NUMERIC "1"
+// Retrieval info: USED_PORT: data0x 0 0 14 0 INPUT NODEFVAL "data0x[13..0]"
+// Retrieval info: USED_PORT: data1x 0 0 14 0 INPUT NODEFVAL "data1x[13..0]"
+// Retrieval info: USED_PORT: result 0 0 14 0 OUTPUT NODEFVAL "result[13..0]"
+// Retrieval info: USED_PORT: sel 0 0 0 0 INPUT NODEFVAL "sel"
+// Retrieval info: CONNECT: @data 0 0 14 0 data0x 0 0 14 0
+// Retrieval info: CONNECT: @data 0 0 14 14 data1x 0 0 14 0
+// Retrieval info: CONNECT: @sel 0 0 1 0 sel 0 0 0 0
+// Retrieval info: CONNECT: result 0 0 14 0 @result 0 0 14 0
+// Retrieval info: GEN_FILE: TYPE_NORMAL ADC_Mux.v TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL ADC_Mux.inc FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL ADC_Mux.cmp FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL ADC_Mux.bsf FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL ADC_Mux_inst.v TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL ADC_Mux_bb.v TRUE
+// Retrieval info: LIB_FILE: lpm

adc_mux/ADC_Mux_inst.v

@@ -0,0 +1,6 @@
+ADC_Mux	ADC_Mux_inst (
+	.data0x ( data0x_sig ),
+	.data1x ( data1x_sig ),
+	.sel ( sel_sig ),
+	.result ( result_sig )
+	);

adc_pll/adc_pll.cmp

@@ -0,0 +1,12 @@
+	component adc_pll is
+		port (
+			refclk   : in  std_logic := 'X'; -- clk
+			rst      : in  std_logic := 'X'; -- reset
+			outclk_0 : out std_logic;        -- clk
+			outclk_1 : out std_logic;        -- clk
+			outclk_2 : out std_logic;        -- clk
+			outclk_3 : out std_logic;        -- clk
+			locked   : out std_logic         -- export
+		);
+	end component adc_pll;
+

adc_pll/adc_pll.ppf

@@ -0,0 +1,16 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<pinplan
+ variation_name="adc_pll"
+ megafunction_name="ALTERA_PLL"
+ intended_family="Arria V"
+ specifies="all_ports">
+ <global>
+  <pin name="refclk" direction="input" scope="external" />
+  <pin name="rst" direction="input" scope="external" />
+  <pin name="outclk_0" direction="output" scope="external" />
+  <pin name="outclk_1" direction="output" scope="external" />
+  <pin name="outclk_2" direction="output" scope="external" />
+  <pin name="outclk_3" direction="output" scope="external" />
+  <pin name="locked" direction="output" scope="external" />
+ </global>
+</pinplan>