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Changed behavior of server, fixed some bugs
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@samdejong86
samdejong86 committed Apr 26, 2018
1 parent dd61598 commit e9e4c5e
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Showing 28 changed files with 81,632 additions and 81,576 deletions.
2 changes: 1 addition & 1 deletion ArriaVADCEthernet_top.cdf
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Expand Up @@ -4,7 +4,7 @@ JedecChain;
DefaultMfr(6E);

P ActionCode(Cfg)
Device PartName(5AGXFB3H4F35) Path("/home/srdejong/ArriaVADCEthernet/output_files/") File("ArriaVADCEthernet_top.sof") MfrSpec(OpMask(1));
Device PartName(5AGXFB3H4F35) Path("/home/srdejong/Arria-V-ADC-Ethernet/output_files/") File("ArriaVADCEthernet_top.sof") MfrSpec(OpMask(1));

ChainEnd;

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125 changes: 62 additions & 63 deletions ArriaVADCEthernet_top.qsf
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7 changes: 4 additions & 3 deletions ArriaVADCEthernet_top.sdc
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Expand Up @@ -19,6 +19,7 @@ derive_pll_clocks -create_base_clocks
set altera_reserved_tck { altera_reserved_tck }
#set clkin_50_fpga { clkin_50_fpga }
create_clock -period 20.00 -name clkin_50 [ get_ports clkin_50 ]
create_clock -period 20.00 -name clkin_50_adc [ get_ports clkin_50_adc ]

#
# these are the generated clocks from jtag and plls that we care about
Expand Down Expand Up @@ -121,9 +122,9 @@ set_input_delay -clock [ get_clocks $altera_reserved_tck ] 10 [ get_ports alte
set_output_delay -clock [ get_clocks $altera_reserved_tck ] 10 [ get_ports altera_reserved_tdo ]

# user pb, dipsw and led
set_input_delay -clock [ get_clocks clkin_50 ] 2 [ get_ports {user_pb[*]} ]
set_input_delay -clock [ get_clocks clkin_50 ] 2 [ get_ports {user_dipsw[*]} ]
set_output_delay -clock [ get_clocks clkin_50 ] 2 [ get_ports {user_led[*]} ]
#set_input_delay -clock [ get_clocks clkin_50 ] 2 [ get_ports {user_pb[*]} ]
#set_input_delay -clock [ get_clocks clkin_50 ] 2 [ get_ports {user_dipsw[*]} ]
#set_output_delay -clock [ get_clocks clkin_50 ] 2 [ get_ports {user_led[*]} ]
set_output_delay -clock [ get_clocks clkin_50 ] 2 [ get_ports {lcd_*} ]
set_input_delay -clock [ get_clocks clkin_50 ] 2 [ get_ports {lcd_data[*]} ]

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745 changes: 371 additions & 374 deletions ArriaVADCEthernet_top.stp
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59 changes: 7 additions & 52 deletions ArriaVADCEthernet_top.sv
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Expand Up @@ -28,9 +28,6 @@ module ArriaVADCEthernet_top
output lcd_en,
output lcd_d_cn,

input [ 3 : 0 ] user_dipsw,
input [ 2 : 0 ] user_pb,
output [ 3 : 0 ] user_led,

input ada_dco,
input adb_dco,
Expand Down Expand Up @@ -133,8 +130,8 @@ wire [15:0] SampleNum;
.cfi_flash_atb_bridge_0_out_tcm_data_out (fm_d),
.cfi_flash_atb_bridge_0_out_tcm_chipselect_n_out (flash_cen),

.enet_pll_locked_export (!cpu_resetn),
.enet_pll_reset_reset (locked_from_the_enet_pll),
.enet_pll_locked_export (locked_from_the_enet_pll),
.enet_pll_reset_reset (!cpu_resetn),

.tse_mac_mac_status_connection_ena_10 (ena_10_from_the_tse_mac),
.tse_mac_mac_status_connection_eth_mode (eth_mode_from_the_tse_mac),
Expand All @@ -158,7 +155,7 @@ wire [15:0] SampleNum;

assign ada_oe = 1'b0;
assign adb_oe = 1'b0;
assign ada_sclk = 1'b0;
assign ad_sclk = 1'b0;
assign ad_sdio = 1'b1;
assign ada_spi_cs = 1'b1;
assign adb_spi_cs = 1'b1;
Expand All @@ -168,7 +165,6 @@ wire sys_clk;
wire sys_clk_90deg;
wire sys_clk_180deg;
wire sys_clk_270deg;
wire ethModuleClk;
wire pll_locked;


Expand All @@ -186,8 +182,8 @@ adc_pll adc_pll(
.outclk_1(sys_clk_90deg),
.outclk_2(sys_clk_180deg),
.outclk_3(sys_clk_270deg),
.outclk_4(ethModuleClk),
.locked(pll_locked)
.locked(pll_locked),
.rst(reset_n)
);

reg delay;
Expand All @@ -199,34 +195,6 @@ wire src1;
wire slp1;
wire del1;

/*
flipSwitch trigsrcFlip(
.clk(ethModuleClk),
.char(adcControl),
.trigChar(8'b01010100),
.out(trigSource)
);
flipSwitch trigslpFlip(
.clk(ethModuleClk),
.char(adcControl),
.trigChar(8'b01010011),
.out(trigSlope)
);
flipSwitch delayFlip(
.clk(ethModuleClk),
.char(adcControl),
.trigChar(8'b01000100),
.out(delay)
);
*/


assign delay = adcControl[3];
assign trigSlope = adcControl[2];
Expand All @@ -235,15 +203,10 @@ wire acquireRequest;
assign acquireRequest = adcControl[0];







wire [15:0] waveNumber;
wire [15:0] lastwavenum;

always @(posedge ethModuleClk) begin
always @(posedge sys_clk) begin

if(acquireRequest==1&&waveNumber!=lastwavenum) //acquire ('A')
acquire=1;
Expand Down Expand Up @@ -299,14 +262,6 @@ ADC_Mux triggerSlopeMux (
);


/*
ADC_Mux TriggerSourceMux (
.data0x ( a2da_data ),
.data1x ( a2db_data ),
.sel ( trigSource ),
.result ( trigSourceData )
);
*/

assign trigger = (trigSource) ? triggerSelf:triggerExt;

Expand Down Expand Up @@ -350,7 +305,7 @@ waveformGenerator waveGen(


getSample samplerModule(
.clk(ethModuleClk),
.clk(sys_clk),
.sampleNum(SampleNum),
.waveform(waveform),
.wavenum(waveNumber),
Expand Down
37 changes: 13 additions & 24 deletions adc_pll.bsf
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Expand Up @@ -21,9 +21,9 @@ agreement for further details.
*/
(header "symbol" (version "1.1"))
(symbol
(rect 0 0 160 304)
(rect 0 0 160 264)
(text "adc_pll" (rect 60 -1 87 11)(font "Arial" (font_size 10)))
(text "inst" (rect 8 288 20 300)(font "Arial" ))
(text "inst" (rect 8 248 20 260)(font "Arial" ))
(port
(pt 0 72)
(input)
Expand Down Expand Up @@ -69,16 +69,9 @@ agreement for further details.
(port
(pt 160 232)
(output)
(text "outclk_4" (rect 0 0 34 12)(font "Arial" (font_size 8)))
(text "outclk_4" (rect 117 221 165 232)(font "Arial" (font_size 8)))
(line (pt 160 232)(pt 112 232)(line_width 1))
)
(port
(pt 160 272)
(output)
(text "locked" (rect 0 0 24 12)(font "Arial" (font_size 8)))
(text "locked" (rect 127 261 163 272)(font "Arial" (font_size 8)))
(line (pt 160 272)(pt 112 272)(line_width 1))
(text "locked" (rect 127 221 163 232)(font "Arial" (font_size 8)))
(line (pt 160 232)(pt 112 232)(line_width 1))
)
(drawing
(text "refclk" (rect 16 43 68 99)(font "Arial" (color 128 0 0)(font_size 9)))
Expand All @@ -93,15 +86,13 @@ agreement for further details.
(text "clk" (rect 97 147 212 304)(font "Arial" (color 0 0 0)))
(text "outclk3" (rect 113 163 268 339)(font "Arial" (color 128 0 0)(font_size 9)))
(text "clk" (rect 97 187 212 384)(font "Arial" (color 0 0 0)))
(text "outclk4" (rect 113 203 268 419)(font "Arial" (color 128 0 0)(font_size 9)))
(text "clk" (rect 97 227 212 464)(font "Arial" (color 0 0 0)))
(text "locked" (rect 113 243 262 499)(font "Arial" (color 128 0 0)(font_size 9)))
(text "export" (rect 82 267 200 544)(font "Arial" (color 0 0 0)))
(text " altera_pll " (rect 118 288 308 586)(font "Arial" ))
(text "locked" (rect 113 203 262 419)(font "Arial" (color 128 0 0)(font_size 9)))
(text "export" (rect 82 227 200 464)(font "Arial" (color 0 0 0)))
(text " altera_pll " (rect 118 248 308 506)(font "Arial" ))
(line (pt 48 32)(pt 112 32)(line_width 1))
(line (pt 112 32)(pt 112 288)(line_width 1))
(line (pt 48 288)(pt 112 288)(line_width 1))
(line (pt 48 32)(pt 48 288)(line_width 1))
(line (pt 112 32)(pt 112 248)(line_width 1))
(line (pt 48 248)(pt 112 248)(line_width 1))
(line (pt 48 32)(pt 48 248)(line_width 1))
(line (pt 49 52)(pt 49 76)(line_width 1))
(line (pt 50 52)(pt 50 76)(line_width 1))
(line (pt 49 92)(pt 49 116)(line_width 1))
Expand All @@ -116,11 +107,9 @@ agreement for further details.
(line (pt 110 172)(pt 110 196)(line_width 1))
(line (pt 111 212)(pt 111 236)(line_width 1))
(line (pt 110 212)(pt 110 236)(line_width 1))
(line (pt 111 252)(pt 111 276)(line_width 1))
(line (pt 110 252)(pt 110 276)(line_width 1))
(line (pt 0 0)(pt 160 0)(line_width 1))
(line (pt 160 0)(pt 160 304)(line_width 1))
(line (pt 0 304)(pt 160 304)(line_width 1))
(line (pt 0 0)(pt 0 304)(line_width 1))
(line (pt 160 0)(pt 160 264)(line_width 1))
(line (pt 0 264)(pt 160 264)(line_width 1))
(line (pt 0 0)(pt 0 264)(line_width 1))
)
)
1 change: 0 additions & 1 deletion adc_pll.cmp
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Expand Up @@ -6,7 +6,6 @@
outclk_1 : out std_logic; -- clk
outclk_2 : out std_logic; -- clk
outclk_3 : out std_logic; -- clk
outclk_4 : out std_logic; -- clk
locked : out std_logic -- export
);
end component adc_pll;
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1 change: 0 additions & 1 deletion adc_pll.ppf
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Expand Up @@ -11,7 +11,6 @@
<pin name="outclk_1" direction="output" scope="external" />
<pin name="outclk_2" direction="output" scope="external" />
<pin name="outclk_3" direction="output" scope="external" />
<pin name="outclk_4" direction="output" scope="external" />
<pin name="locked" direction="output" scope="external" />
</global>
</pinplan>
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