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Restructured code, modified testbenches
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@@ -5,7 +5,7 @@ incremental_db/* | |
| *# | ||
| output_files/* | ||
| greybox_tmp/* | ||
| *greybox_tmp/* | ||
| greybox_tmp* | ||
| *.qws | ||
| *.summary | ||
| *.rpt | ||
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| // megafunction wizard: %LPM_MUX% | ||
| // GENERATION: STANDARD | ||
| // VERSION: WM1.0 | ||
| // MODULE: LPM_MUX | ||
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| // ============================================================ | ||
| // File Name: ADC_Mux.v | ||
| // Megafunction Name(s): | ||
| // LPM_MUX | ||
| // | ||
| // Simulation Library Files(s): | ||
| // lpm | ||
| // ============================================================ | ||
| // ************************************************************ | ||
| // THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! | ||
| // | ||
| // 16.1.0 Build 196 10/24/2016 SJ Standard Edition | ||
| // ************************************************************ | ||
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| //Copyright (C) 2016 Intel Corporation. All rights reserved. | ||
| //Your use of Intel Corporation's design tools, logic functions | ||
| //and other software and tools, and its AMPP partner logic | ||
| //functions, and any output files from any of the foregoing | ||
| //(including device programming or simulation files), and any | ||
| //associated documentation or information are expressly subject | ||
| //to the terms and conditions of the Intel Program License | ||
| //Subscription Agreement, the Intel Quartus Prime License Agreement, | ||
| //the Intel MegaCore Function License Agreement, or other | ||
| //applicable license agreement, including, without limitation, | ||
| //that your use is for the sole purpose of programming logic | ||
| //devices manufactured by Intel and sold by Intel or its | ||
| //authorized distributors. Please refer to the applicable | ||
| //agreement for further details. | ||
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| //lpm_mux DEVICE_FAMILY="Arria V" LPM_SIZE=2 LPM_WIDTH=14 LPM_WIDTHS=1 data result sel | ||
| //VERSION_BEGIN 16.1 cbx_lpm_mux 2016:10:19:21:26:20:SJ cbx_mgl 2016:10:19:22:10:30:SJ VERSION_END | ||
| // synthesis VERILOG_INPUT_VERSION VERILOG_2001 | ||
| // altera message_off 10463 | ||
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| //synthesis_resources = lut 5 | ||
| //synopsys translate_off | ||
| `timescale 1 ps / 1 ps | ||
| //synopsys translate_on | ||
| module ADC_Mux_mux | ||
| ( | ||
| data, | ||
| result, | ||
| sel) /* synthesis synthesis_clearbox=1 */; | ||
| input [27:0] data; | ||
| output [13:0] result; | ||
| input [0:0] sel; | ||
| `ifndef ALTERA_RESERVED_QIS | ||
| // synopsys translate_off | ||
| `endif | ||
| tri0 [27:0] data; | ||
| tri0 [0:0] sel; | ||
| `ifndef ALTERA_RESERVED_QIS | ||
| // synopsys translate_on | ||
| `endif | ||
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| wire wire_l1_w0_n0_mux_dataout; | ||
| wire wire_l1_w10_n0_mux_dataout; | ||
| wire wire_l1_w11_n0_mux_dataout; | ||
| wire wire_l1_w12_n0_mux_dataout; | ||
| wire wire_l1_w13_n0_mux_dataout; | ||
| wire wire_l1_w1_n0_mux_dataout; | ||
| wire wire_l1_w2_n0_mux_dataout; | ||
| wire wire_l1_w3_n0_mux_dataout; | ||
| wire wire_l1_w4_n0_mux_dataout; | ||
| wire wire_l1_w5_n0_mux_dataout; | ||
| wire wire_l1_w6_n0_mux_dataout; | ||
| wire wire_l1_w7_n0_mux_dataout; | ||
| wire wire_l1_w8_n0_mux_dataout; | ||
| wire wire_l1_w9_n0_mux_dataout; | ||
| wire [27:0] data_wire; | ||
| wire [13:0] result_wire_ext; | ||
| wire [0:0] sel_wire; | ||
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| assign wire_l1_w0_n0_mux_dataout = (sel_wire[0] === 1'b1) ? data_wire[14] : data_wire[0]; | ||
| assign wire_l1_w10_n0_mux_dataout = (sel_wire[0] === 1'b1) ? data_wire[24] : data_wire[10]; | ||
| assign wire_l1_w11_n0_mux_dataout = (sel_wire[0] === 1'b1) ? data_wire[25] : data_wire[11]; | ||
| assign wire_l1_w12_n0_mux_dataout = (sel_wire[0] === 1'b1) ? data_wire[26] : data_wire[12]; | ||
| assign wire_l1_w13_n0_mux_dataout = (sel_wire[0] === 1'b1) ? data_wire[27] : data_wire[13]; | ||
| assign wire_l1_w1_n0_mux_dataout = (sel_wire[0] === 1'b1) ? data_wire[15] : data_wire[1]; | ||
| assign wire_l1_w2_n0_mux_dataout = (sel_wire[0] === 1'b1) ? data_wire[16] : data_wire[2]; | ||
| assign wire_l1_w3_n0_mux_dataout = (sel_wire[0] === 1'b1) ? data_wire[17] : data_wire[3]; | ||
| assign wire_l1_w4_n0_mux_dataout = (sel_wire[0] === 1'b1) ? data_wire[18] : data_wire[4]; | ||
| assign wire_l1_w5_n0_mux_dataout = (sel_wire[0] === 1'b1) ? data_wire[19] : data_wire[5]; | ||
| assign wire_l1_w6_n0_mux_dataout = (sel_wire[0] === 1'b1) ? data_wire[20] : data_wire[6]; | ||
| assign wire_l1_w7_n0_mux_dataout = (sel_wire[0] === 1'b1) ? data_wire[21] : data_wire[7]; | ||
| assign wire_l1_w8_n0_mux_dataout = (sel_wire[0] === 1'b1) ? data_wire[22] : data_wire[8]; | ||
| assign wire_l1_w9_n0_mux_dataout = (sel_wire[0] === 1'b1) ? data_wire[23] : data_wire[9]; | ||
| assign | ||
| data_wire = {data}, | ||
| result = result_wire_ext, | ||
| result_wire_ext = {wire_l1_w13_n0_mux_dataout, wire_l1_w12_n0_mux_dataout, wire_l1_w11_n0_mux_dataout, wire_l1_w10_n0_mux_dataout, wire_l1_w9_n0_mux_dataout, wire_l1_w8_n0_mux_dataout, wire_l1_w7_n0_mux_dataout, wire_l1_w6_n0_mux_dataout, wire_l1_w5_n0_mux_dataout, wire_l1_w4_n0_mux_dataout, wire_l1_w3_n0_mux_dataout, wire_l1_w2_n0_mux_dataout, wire_l1_w1_n0_mux_dataout, wire_l1_w0_n0_mux_dataout}, | ||
| sel_wire = {sel[0]}; | ||
| endmodule //ADC_Mux_mux | ||
| //VALID FILE | ||
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| // synopsys translate_off | ||
| `timescale 1 ps / 1 ps | ||
| // synopsys translate_on | ||
| module ADC_Mux ( | ||
| data0x, | ||
| data1x, | ||
| sel, | ||
| result)/* synthesis synthesis_clearbox = 1 */; | ||
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| input [13:0] data0x; | ||
| input [13:0] data1x; | ||
| input sel; | ||
| output [13:0] result; | ||
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| wire [13:0] sub_wire0; | ||
| wire [13:0] sub_wire3 = data1x[13:0]; | ||
| wire [13:0] result = sub_wire0[13:0]; | ||
| wire [13:0] sub_wire1 = data0x[13:0]; | ||
| wire [27:0] sub_wire2 = {sub_wire3, sub_wire1}; | ||
| wire sub_wire4 = sel; | ||
| wire sub_wire5 = sub_wire4; | ||
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| ADC_Mux_mux ADC_Mux_mux_component ( | ||
| .data (sub_wire2), | ||
| .sel (sub_wire5), | ||
| .result (sub_wire0)); | ||
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| endmodule | ||
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| // ============================================================ | ||
| // CNX file retrieval info | ||
| // ============================================================ | ||
| // Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Arria V" | ||
| // Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "1" | ||
| // Retrieval info: PRIVATE: new_diagram STRING "1" | ||
| // Retrieval info: LIBRARY: lpm lpm.lpm_components.all | ||
| // Retrieval info: CONSTANT: LPM_SIZE NUMERIC "2" | ||
| // Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_MUX" | ||
| // Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "14" | ||
| // Retrieval info: CONSTANT: LPM_WIDTHS NUMERIC "1" | ||
| // Retrieval info: USED_PORT: data0x 0 0 14 0 INPUT NODEFVAL "data0x[13..0]" | ||
| // Retrieval info: USED_PORT: data1x 0 0 14 0 INPUT NODEFVAL "data1x[13..0]" | ||
| // Retrieval info: USED_PORT: result 0 0 14 0 OUTPUT NODEFVAL "result[13..0]" | ||
| // Retrieval info: USED_PORT: sel 0 0 0 0 INPUT NODEFVAL "sel" | ||
| // Retrieval info: CONNECT: @data 0 0 14 0 data0x 0 0 14 0 | ||
| // Retrieval info: CONNECT: @data 0 0 14 14 data1x 0 0 14 0 | ||
| // Retrieval info: CONNECT: @sel 0 0 1 0 sel 0 0 0 0 | ||
| // Retrieval info: CONNECT: result 0 0 14 0 @result 0 0 14 0 | ||
| // Retrieval info: GEN_FILE: TYPE_NORMAL ADC_Mux.v TRUE | ||
| // Retrieval info: GEN_FILE: TYPE_NORMAL ADC_Mux.inc FALSE | ||
| // Retrieval info: GEN_FILE: TYPE_NORMAL ADC_Mux.cmp FALSE | ||
| // Retrieval info: GEN_FILE: TYPE_NORMAL ADC_Mux.bsf FALSE | ||
| // Retrieval info: GEN_FILE: TYPE_NORMAL ADC_Mux_inst.v TRUE | ||
| // Retrieval info: GEN_FILE: TYPE_NORMAL ADC_Mux_bb.v TRUE | ||
| // Retrieval info: GEN_FILE: TYPE_NORMAL ADC_Mux_syn.v TRUE | ||
| // Retrieval info: LIB_FILE: lpm |
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