[all] Code style fixes.

Trailing whitespace, include guard, and nullptr.

misc/Vagrantfile

@@ -13,7 +13,7 @@ Vagrant::Config.run do |config|
     export DEBIAN_FRONTEND=noninteractive
     apt-get -y update
     # apt-get -y dist-upgrade
-    
+
     # zsim dependencies
     apt-get -y install build-essential g++ git scons
     apt-get -y install libelfg0-dev libhdf5-serial-dev libconfig++-dev

misc/hooks/test.java

@@ -1,6 +1,6 @@
 
-public class test { 
-    public static void main(String[] args) { 
+public class test {
+    public static void main(String[] args) {
         System.out.println("Java test");
         zsim.roi_begin();
         for (int i = 0; i < 42; i++) zsim.heartbeat();

misc/patchRoot/cpuinfo.template

@@ -1,4 +1,4 @@
-processor	: $CPU 
+processor	: $CPU
 vendor_id	: GenuineIntel
 cpu family	: 6
 model		: 15

src/access_tracing.cpp

@@ -111,7 +111,7 @@ AccessTraceWriter::AccessTraceWriter(g_string _fname, uint32_t numChildren) : fn
 
     hid_t fid = H5Fcreate(fname.c_str(), H5F_ACC_TRUNC, H5P_DEFAULT, H5P_DEFAULT);
     if (fid == H5I_INVALID_HID) panic("Could not create HDF5 file %s", fname.c_str());
-    
+
     // HACK: We want to use the SHUF filter... create the raw dataset instead of the packet table
     // hid_t table = H5PTcreate_fl(fid, "accs", recType, PT_CHUNKSIZE, 9);
     // if (table == H5I_INVALID_HID) panic("Could not create HDF5 packet table");

src/access_tracing.h

@@ -87,7 +87,7 @@ class AccessTraceWriter : public GlobAlloc {
 
     public:
         AccessTraceWriter(g_string fname, uint32_t numChildren);
-        
+
         inline void write(AccessRecord& acc) {
             buf[cur++] = {acc.lineAddr, acc.reqCycle, acc.latency, (uint16_t) acc.childId, (uint8_t) acc.type};
             if (unlikely(cur == max)) {

src/breakdown_stats.h

@@ -23,6 +23,9 @@
  * this program. If not, see <http://www.gnu.org/licenses/>.
  */
 
+#ifndef BREAKDOWN_STATS_H_
+#define BREAKDOWN_STATS_H_
+
 #include "bithacks.h"
 #include "stats.h"
 #include "zsim.h"
@@ -67,3 +70,4 @@ class CycleBreakdownStat : public VectorCounter {
         }
 };
 
+#endif  // BREAKDOWN_STATS_H_

src/cpuenum.h

@@ -48,7 +48,7 @@ inline std::vector<bool> cpuenumMask(uint32_t pid) {
     if (zinfo->perProcessCpuEnum) {
         res.resize(cpuenumNumCpus(pid));
         for (uint32_t i = 0; i < res.size(); i++) res[i] = true;
-    } else { 
+    } else {
         const g_vector<bool>& mask = zinfo->procArray[pid]->getMask();
         res.resize(mask.size());
         for (uint32_t i = 0; i < res.size(); i++) res[i] = mask[i];

src/ddr_mem.cpp

@@ -296,7 +296,7 @@ DDRMemory::AddrLoc DDRMemory::mapLineAddr(Address lineAddr) {
 void DDRMemory::enqueue(DDRMemoryAccEvent* ev, uint64_t sysCycle) {
     uint64_t memCycle = sysToMemCycle(sysCycle);
     DEBUG("%ld: enqueue() addr 0x%lx wr %d", memCycle, ev->getAddr(), ev->isWrite());
-    
+
     // Create request
     Request ovfReq;
     bool overflow = rdQueue.full() || wrQueue.full();
@@ -320,7 +320,7 @@ void DDRMemory::enqueue(DDRMemoryAccEvent* ev, uint64_t sysCycle) {
 
         // If needed, schedule an event to handle this new request
         if (!req->prev /* first in bank */) {
-            uint64_t minSchedCycle = std::max(memCycle, minRespCycle - tCL - tBL);  
+            uint64_t minSchedCycle = std::max(memCycle, minRespCycle - tCL - tBL);
             if (nextSchedCycle > minSchedCycle) minSchedCycle = std::max(minSchedCycle, findMinCmdCycle(*req));
             if (nextSchedCycle > minSchedCycle) {
                 if (nextSchedEvent) nextSchedEvent->annul();
@@ -338,11 +338,11 @@ void DDRMemory::enqueue(DDRMemoryAccEvent* ev, uint64_t sysCycle) {
                 nextSchedEvent->enqueue(enqSysCycle);
                 nextSchedCycle = minSchedCycle;
             }
-        } 
+        }
     }
 }
 
-void DDRMemory::queue(Request* req, uint64_t memCycle) {    
+void DDRMemory::queue(Request* req, uint64_t memCycle) {
     // If it's a write, respond to it immediately
     if (req->write) {
         auto ev = req->ev;
@@ -352,7 +352,7 @@ void DDRMemory::queue(Request* req, uint64_t memCycle) {
         uint64_t respCycle = memToSysCycle(memCycle) + minWrLatency;
         ev->done(respCycle - preDelay - postDelayWr);
     }
-    
+
     req->arrivalCycle = memCycle;  // if this comes from the overflow queue, update
 
     // Test: Skip writes
@@ -437,7 +437,7 @@ uint64_t DDRMemory::tick(uint64_t sysCycle) {
         overflowQueue.pop_front();
 
         queue(req, memCycle);
-        
+
         // This request may be schedulable before trySchedule's minSchedCycle
         if (!req->prev /*first in bank queue*/) {
             uint64_t minQueuedSchedCycle = std::max(memCycle, minRespCycle - tCL - tBL);
@@ -567,7 +567,7 @@ uint64_t DDRMemory::trySchedule(uint64_t curCycle, uint64_t sysCycle) {
 
         uint64_t actCycle = std::max(r->arrivalCycle, std::max(preCycle + tRP, bank.lastActCycle + tRRD));
         actCycle = std::max(actCycle, rankActWindows[r->loc.rank].minActCycle() + tFAW);
-        
+
         // Record ACT
         bank.open = true;
         bank.openRow = r->loc.row;
@@ -602,10 +602,10 @@ uint64_t DDRMemory::trySchedule(uint64_t curCycle, uint64_t sysCycle) {
     if (r->ev) {
         auto ev = r->ev;
         assert(!ev->isWrite() && !r->write);  // reads only
-        
+
         uint64_t doneSysCycle = memToSysCycle(minRespCycle) + controllerSysLatency;
         assert(doneSysCycle >= sysCycle);
-        
+
         ev->release();
         ev->done(doneSysCycle - preDelay - postDelayRd);
 
@@ -623,7 +623,7 @@ uint64_t DDRMemory::trySchedule(uint64_t curCycle, uint64_t sysCycle) {
     }
 
     DEBUG("Served 0x%lx lat %ld clocks", r->addr, minRespCycle-curCycle);
-    
+
     // Dequeue this req
     queue.remove(ir);
     (isWriteQueue? bank.wrReqs : bank.rdReqs).pop_front();
@@ -651,7 +651,7 @@ void DDRMemory::refresh(uint64_t sysCycle) {
             bank.open = false;
         }
     }
-    
+
     DEBUG("Refresh %ld start %ld done %ld", memCycle, minRefreshCycle, refreshDoneCycle);
 }
 
@@ -728,7 +728,7 @@ void DDRMemory::initTech(const char* techName) {
         // even 32 bytes is pushing it, 32B probably calls for coalescing buffers
         panic("Unsupported line size %d", lineSize);
     }
-    
+
     memFreqKHz = (uint64_t)(1e9/tCK/1e3);
 }
 

src/ddr_mem.h

@@ -135,7 +135,7 @@ class SchedEvent;
 // Single-channel controller. For multiple channels, use multiple controllers.
 class DDRMemory : public MemObject {
     private:
-        
+
         struct AddrLoc {
             uint64_t row;
             uint32_t bank;
@@ -167,7 +167,7 @@ class DDRMemory : public MemObject {
             uint64_t minPreCycle;   // if !open, time of last PRE; if open, min cycle PRE can be issued
             uint64_t lastActCycle;  // cycle of last ACT command
             uint64_t lastCmdCycle;  // RD/WR command, used for refreshes only
-            
+
             uint64_t curRowHits;    // row hits on the currently opened row
 
             InList<Request> rdReqs;
@@ -224,7 +224,7 @@ class DDRMemory : public MemObject {
 
         g_vector< g_vector<Bank> > banks; // indexed by rank, bank
         g_vector<ActWindow> rankActWindows;
-        
+
         // Event scheduling
         SchedEvent* nextSchedEvent;
         uint64_t nextSchedCycle;
@@ -279,12 +279,12 @@ class DDRMemory : public MemObject {
 
     private:
         AddrLoc mapLineAddr(Address lineAddr);
-        
+
         void queue(Request* req, uint64_t memCycle);
-        
+
         inline uint64_t trySchedule(uint64_t curCycle, uint64_t sysCycle);
         uint64_t findMinCmdCycle(const Request& r) const;
-        
+
         void initTech(const char* tech);
 };
 

src/detailed_mem.cpp

@@ -845,7 +845,7 @@ uint64_t MemChannelBase::GetBackGroundEnergy(uint64_t memCycle, uint64_t lastMem
 MemSchedulerDefault::MemSchedulerDefault(uint32_t id, MemParam* mParam, MemChannelBase* mChnl)
     : MemSchedulerBase(id, mParam, mChnl)
 {
-    prioritizedAccessType = READ; 
+    prioritizedAccessType = READ;
     wrQueueSize = mParam->schedulerQueueCount;
     wrQueueHighWatermark = mParam->schedulerQueueCount * 2 / 3;
     wrQueueLowWatermark = mParam->schedulerQueueCount * 1 / 3;
@@ -1049,7 +1049,7 @@ void MemControllerBase::enqueue(MemAccessEventBase* ev, uint64_t cycle) {
     if (mParam->schedulerQueueCount == 0) {
         MemAccessType type = ev->getType();
         uint64_t startCycle = cycle - preDelay[type] + mParam->controllerLatency;
-        // FIXME: Shouldn't we use the next memCycle following startCycle as the 
+        // FIXME: Shouldn't we use the next memCycle following startCycle as the
         // starting cycle of the dram request?
         uint64_t latency = LatencySimulate(ev->getAddr(), startCycle, type);
         ev->done(cycle + latency - minLatency[type] + mParam->controllerLatency);

src/detailed_mem.h

@@ -23,8 +23,8 @@
  * this program. If not, see <http://www.gnu.org/licenses/>.
  */
 
-#ifndef __DETAILED_MEM_H__
-#define __DETAILED_MEM_H__
+#ifndef DETAILED_MEM_H_
+#define DETAILED_MEM_H_
 
 #include "detailed_mem_params.h"
 #include "g_std/g_string.h"
@@ -206,8 +206,8 @@ class MemSchedulerBase : public GlobAlloc {
         // HK: I hope there's a good reason to be using a reference to a pointer here
         // Don't know the code enough at the moment to be able to tell.
         //
-        // Hmm...so upon further investigation it looks like all of these arguments are 
-        // written by the function. I am not a big fan of passing WRITE arguments by 
+        // Hmm...so upon further investigation it looks like all of these arguments are
+        // written by the function. I am not a big fan of passing WRITE arguments by
         // reference. Even more distrubingly, MemSchedQueueElem uses its MemAccessEventBase
         // member in a weird way, with the member var being nullptr signifying something (I don't
         // know what yet). Will look into this further
@@ -345,4 +345,4 @@ class MemAccessEventBase : public TimingEvent {
         Address getAddr() const { return addr; }
 };
 
-#endif
+#endif  // DETAILED_MEM_H_

src/detailed_mem_params.h

@@ -23,8 +23,8 @@
  * this program. If not, see <http://www.gnu.org/licenses/>.
  */
 
-#ifndef __DETAILED_MEM_PARAMS_H__
-#define __DETAILED_MEM_PARAMS_H__
+#ifndef DETAILED_MEM_PARAMS_H_
+#define DETAILED_MEM_PARAMS_H_
 
 #include "g_std/g_string.h"
 #include "config.h"
@@ -144,4 +144,4 @@ class MemParam : public GlobAlloc{
         uint32_t writeTermPin;
 };
 
-#endif /* __DETAILED_MEM_PARAMS_H__ */
+#endif  // DETAILED_MEM_PARAMS_H_

src/dumptrace.cpp

@@ -42,7 +42,7 @@ int main(int argc, const char* argv[]) {
 
     gm_init(32<<20 /*32 MB, should be enough*/);
     AccessTraceReader tr(argv[1]);
-    
+
     info("%12s %6s %6s %20s %10s", "Cycle", "Src", "Type", "LineAddr", "Latency");
     while(!tr.empty()) {
         AccessRecord acc = tr.read();

src/g_heap/dlmalloc.h.c

@@ -46,11 +46,11 @@
  * mparams data structure. In zsim, these are *per process*. This is totally
  * fine, as the global lock is used to 1) Protect mparams initialization, and
  * 2) Synchronize calls to the system allocator (mmap, etc). Since we initialize
- * mparams per process and do not ever get memory from the system, this is fine. 
+ * mparams per process and do not ever get memory from the system, this is fine.
  *
  * The only code change is to set the magic number in init_mparams to be fixed
  * instead of randomly derived. The reason is that there is one mparams per
- * process, so it is initialized multiple times. 
+ * process, so it is initialized multiple times.
  */
 
 /*
@@ -1419,7 +1419,7 @@ LONG __cdecl _InterlockedExchange(LONG volatile *Target, LONG Value);
 
 /* Declarations for bit scanning on win32 */
 #if defined(_MSC_VER) && _MSC_VER>=1300
-#ifndef BitScanForward	/* Try to avoid pulling in WinNT.h */
+#ifndef BitScanForward    /* Try to avoid pulling in WinNT.h */
 #ifdef __cplusplus
 extern "C" {
 #endif /* __cplusplus */

src/g_std/stl_galloc.h

@@ -57,7 +57,7 @@ class StlGlobAlloc {
         pointer address(reference x) const { return &x; }
         const_pointer address(const_reference x) const { return &x; }
         StlGlobAlloc<T>& operator=(const StlGlobAlloc&) { return *this; }
-        
+
 
         // Construct/destroy
         // gcc keeps changing these interfaces. See /usr/include/c++/4.8/ext/new_allocator.h

src/hash.cpp

@@ -169,5 +169,5 @@ uint64_t SHA1HashFamily::hash(uint32_t id, uint64_t val) {
     panic("???");
     return 0;
 }
- 
+
 #endif  // _WITH_POLARSSL_

src/log.h

@@ -69,9 +69,9 @@ extern FILE* logFdErr;
 /* Set per-process header for log/info/warn/panic messages
  * Calling this is not needed (the default header is ""),
  * but it helps in multi-process runs
- * If file is NULL or InitLog is not called, logs to stdout/stderr
+ * If file is nullptr or InitLog is not called, logs to stdout/stderr
  */
-void InitLog(const char* header, const char* file = NULL);
+void InitLog(const char* header, const char* file = nullptr);
 
 /* Helper class to print expression with values
  * Inpired by Phil Nash's CATCH, https://github.com/philsquared/Catch

src/ooo_core.cpp

@@ -179,7 +179,7 @@ inline void OOOCore::bbl(Address bblAddr, BblInfo* bblInfo) {
     // Run dispatch/IW
     for (uint32_t i = 0; i < bbl->uops; i++) {
         DynUop* uop = &(bbl->uop[i]);
-        
+
         // Decode stalls
         uint32_t decDiff = uop->decCycle - prevDecCycle;
         decodeCycle = MAX(decodeCycle + decDiff, uopQueue.minAllocCycle());
@@ -303,7 +303,7 @@ inline void OOOCore::bbl(Address bblAddr, BblInfo* bblInfo) {
 
                     // Wait for all previous store addresses to be resolved (not just ours :))
                     dispatchCycle = MAX(lastStoreAddrCommitCycle+1, dispatchCycle);
-                    
+
                     Address addr = storeAddrs[storeIdx++];
                     uint64_t reqSatisfiedCycle = l1d->store(addr, dispatchCycle) + L1D_LAT;
                     cRec.record(curCycle, dispatchCycle, reqSatisfiedCycle);
@@ -398,7 +398,7 @@ inline void OOOCore::bbl(Address bblAddr, BblInfo* bblInfo) {
          * (28 uops), IW (36 uops), and 16B instr length predecoder buffer. At
          * ~3.5 bytes/instr, 1.2 uops/instr, this is about 5 64-byte lines.
          */
-         
+
         // info("Mispredicted branch, %ld %ld %ld | %ld %ld", decodeCycle, curCycle, lastCommitCycle,
         //         lastCommitCycle-decodeCycle, lastCommitCycle-curCycle);
         Address wrongPathAddr = branchTaken? branchNotTakenNpc : branchTakenNpc;

src/ooo_core.h

@@ -72,7 +72,7 @@ class BranchPredictorPAg {
             uint32_t bhsrMask = (1 << NB) - 1;
             uint32_t histMask = (1 << HB) - 1;
             uint32_t phtMask  = (1 << LB) - 1;
-           
+
             // Predict
             // uint32_t bhsrIdx = ((uint32_t)( branchPc ^ (branchPc >> NB) ^ (branchPc >> 2*NB) )) & bhsrMask;
             uint32_t bhsrIdx = ((uint32_t)( branchPc >> 1)) & bhsrMask;
@@ -81,7 +81,7 @@ class BranchPredictorPAg {
             // Shift-XOR-mask to fit in PHT
             phtIdx ^= (phtIdx & ~phtMask) >> (HB - LB); // take the [HB-1, LB] bits of bshr, XOR with [LB-1, ...] bits
             phtIdx &= phtMask;
-            
+
             // If uncommented, behaves like a global history predictor
             // bhsrIdx = 0;
             // phtIdx = (bhsr[bhsrIdx] ^ ((uint32_t)branchPc)) & phtMask;
@@ -411,7 +411,7 @@ class OOOCore : public Core {
         Address branchNotTakenNpc;
 
         uint64_t decodeCycle;
-        CycleQueue<28> uopQueue;  // models issue queue 
+        CycleQueue<28> uopQueue;  // models issue queue
 
         uint64_t instrs, uops, bbls, approxInstrs, mispredBranches;
 

src/proc_stats.h

@@ -51,7 +51,7 @@ class ProcStats : public GlobAlloc {
         void notifyDeschedule();
 
     private:
-        Stat* replStat(Stat* s, const char* name = NULL, const char* desc = NULL);
+        Stat* replStat(Stat* s, const char* name = nullptr, const char* desc = nullptr);
 
         void update();  // transparent
 };