CHERI encodings and CSRs

csrs.csv

@@ -240,7 +240,14 @@
 0x3ed, "pmpaddr61"
 0x3ee, "pmpaddr62"
 0x3ef, "pmpaddr63"
+0x417, "jvtc"
+0x505, "stvecc"
+0x540, "sscratchc"
+0x541, "sepcc"
 0x747, "mseccfg"
+0x760, "mscratchc"
+0x761, "mepcc"
+0x765, "mtvecc"
 0x7a0, "tselect"
 0x7a1, "tdata1"
 0x7a2, "tdata2"
@@ -253,6 +260,11 @@
 0x7b1, "dpc"
 0x7b2, "dscratch0"
 0x7b3, "dscratch1"
+0x7b9, "dpcc"
+0x7ba, "dscratch0c"
+0x7bb, "dscratch1c"
+0x7bc, "dddc"
+0x7bd, "dinfcap"
 0xB00, "mcycle"
 0xB02, "minstret"
 0xB03, "mhpmcounter3"

unratified/rv64_cheri

@@ -0,0 +1,51 @@
+lc                 rd rs1          imm12   14..12=4 6..2=0x03 1..0=3
+sc                 imm12hi rs1 rs2 imm12lo 14..12=4 6..2=0x08 1..0=3
+
+#need to ADDIW
+caddi             rd rs1 imm12            14..12=2 6..2=0x06 1..0=3
+#5-bit immediate and 25 says whether to shift it
+scbndsi           rd rs1 imm5 31..26=1    14..12=5 6..2=0x04 1..0=3
+
+#if rs2=x0 decode as cmove
+cadd              rd rs1 rs2      31..25=6 14..12=0 6..2=0x0C 1..0=3
+scaddr            rd rs1 rs2      31..25=6 14..12=1 6..2=0x0C 1..0=3
+acperm            rd rs1 rs2      31..25=6 14..12=2 6..2=0x0C 1..0=3
+schi              rd rs1 rs2      31..25=6 14..12=3 6..2=0x0C 1..0=3
+sceq              rd rs1 rs2      31..25=6 14..12=4 6..2=0x0C 1..0=3
+cbld              rd rs1 rs2      31..25=6 14..12=5 6..2=0x0C 1..0=3
+cscc              rd rs1 rs2      31..25=6 14..12=6 6..2=0x0C 1..0=3
+scmode            rd rs1 rs2      31..25=6 14..12=7 6..2=0x0C 1..0=3
+
+scbnds            rd rs1 rs2      31..25=7 14..12=0 6..2=0x0C 1..0=3
+scbndsr           rd rs1 rs2      31..25=7 14..12=1 6..2=0x0C 1..0=3
+
+gctag             rd rs1 31..25=8 24..20=0 14..12=0 6..2=0x0C 1..0=3
+gcperm            rd rs1 31..25=8 24..20=1 14..12=0 6..2=0x0C 1..0=3
+gchi              rd rs1 31..25=8 24..20=4 14..12=0 6..2=0x0C 1..0=3
+gcbase            rd rs1 31..25=8 24..20=5 14..12=0 6..2=0x0C 1..0=3
+gclen             rd rs1 31..25=8 24..20=6 14..12=0 6..2=0x0C 1..0=3
+cram              rd rs1 31..25=8 24..20=7 14..12=0 6..2=0x0C 1..0=3
+sentry            rd rs1 31..25=8 24..20=8 14..12=0 6..2=0x0C 1..0=3
+
+modesw            31..25=9 24..15=0 14..12=1 11..7=0 6..2=0x0C 1..0=3
+
+#adjacent to c.not
+c.modesw          15..13=4 12..10=7 9..7=0 6..5=3 4..2=7 1..0=1
+
+#adjacent to JALR
+jalr.mode         rd rs1   31..20=0 14..12=1 6..2=0x19 1..0=3
+
+#adjacent to sh[123]add
+sh4add     rd rs1 rs2 31..25=16 14..12=7 6..2=0x0C 1..0=3
+
+#adjacent to sh[123]add.uw
+sh4add.uw  rd rs1 rs2 31..25=16 14..12=7 6..2=0x0E 1..0=3
+
+#regular encodings - will become a separate extension
+lr.b        rd rs1 24..20=0 aq rl 31..29=0 28..27=2 14..12=0 6..2=0x0B 1..0=3
+lr.h        rd rs1 24..20=0 aq rl 31..29=0 28..27=2 14..12=1 6..2=0x0B 1..0=3
+sc.b        rd rs1 rs2      aq rl 31..29=0 28..27=3 14..12=0 6..2=0x0B 1..0=3
+sc.h        rd rs1 rs2      aq rl 31..29=0 28..27=3 14..12=1 6..2=0x0B 1..0=3
+
+#regular encoding
+amoswap.c   rd rs1 rs2      aq rl 31..29=0 28..27=1 14..12=4 6..2=0x0B 1..0=3