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Remove Smaiae extension #622 #640

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0af613e
Remove Smaiae extension riscv#622
mark-honman Oct 20, 2025
5037009
tidied up AIA area note
mark-honman Oct 20, 2025
f041ac9
Update aclic.adoc
mark-honman Oct 27, 2025
d07ce1d
Update src/aclic.adoc
christian-herber-nxp Oct 27, 2025
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51 changes: 19 additions & 32 deletions src/aclic.adoc
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Original file line number Diff line number Diff line change
Expand Up @@ -180,7 +180,6 @@ The table below provides a summary of the ACLIC extensions.
[%autowidth]
|===
| Extension Name | Description
| Smaiae | Advanced Interrupt Architecture for Embedded Systems
| Smaclic | Advanced Core Local Interrupt Controller at Machine level
| Ssaclic | Advanced Core Local Interrupt Controller at Supervisor level
| Smivt | Support for interrupt vector table at Machine level
Expand All @@ -202,18 +201,17 @@ Each row contains the dependencies of the extension named in the first column.

[%autowidth]
|===
| Extension Name | Sm | Ss | Smcsrind | Sscsrind | Smaiae | Smnip
| Smivt | x | | | | |
| Ssivt | | x | | | |
| Smcsps | x | | | | |
| Sscsps | | x | | | |
| Smtp | (x)| (x)| | | |
| Smaiae | x | (x)| x | (x) | |
| Smaclic | | | | | x |
| Ssaclic | | | | | x |
| Smnip | | | | | x |
| Ssnip | | | | | | x
| Smehv | | | | | | x
| Extension Name | Sm | Ss | Smcsrind | Sscsrind | Smaclic | Smnip
| Smivt | x | | | | |
| Ssivt | | x | | | |
| Smcsps | x | | | | |
| Sscsps | | x | | | |
| Smtp | (x)| (x)| | | |
| Smaclic | x | | x | | |
| Ssaclic | | x | | x | x |
| Smnip | | | | | x |
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needs the AIA dependency

| Ssnip | | | | | | x
| Smehv | | | | | | x
|===

In this table (x) denotes a dependency that is valid,
Expand All @@ -222,25 +220,6 @@ if the corresponding privilege mode is implemented in the hart.
NOTE: The extensions defined here are orthogonal to the NMI and RNMI
mechanisms. Their behavior is unchanged by the extensions of ACLIC.

== Advanced Interrupt Architecture for Embedded Systems (Smaiae)

The Smaia extension encompasses all added CSRs
and all modifications to interrupt response behavior
that the AIA specifies for a hart,
over all privilege levels.

The Smaiae extension is a subset of Smaia.
To limit the implementation cost,
the interrupt filtering and virtual interrupts are not supported.

Specifically, `xvip` and `xvien` are read-only 0.
When XLEN=32, `xviph` and `xvienh` are also read-only 0.

NOTE: While other features of AIA like IMSIC or programmable IPRIO
might also not be needed resource constraint systems,
These are already controlled by WARL registers,
so implementations can already choose to not support these.

== Advanced Core Local Interrupt Controller (Smaclic and Ssaclic)

The Smaclic and Ssaclic extensions depend on the Smaiae extension.
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This needs to be removed.

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Instead, dependence on indirect CSR needs to be added.

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The Smnip section is also stated to have an Smaiae dependency. I have changed that to an Smaclic dependency because the section on State enables refers to an ACLIC bit.

However as written Smnip only really depends on AIA; I'll open an issue to discuss whether it should be an extension in its own right.

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It should only depend on AIA. The state enable bit is a secondary concern. We will have to see down the road if every extension gets its own state enable bit. But I do not view this bit as only present when Smaclic is present.

Expand Down Expand Up @@ -429,6 +408,14 @@ and the conditions for a virtual instruction exception apply,
in which case a virtual instruction exception is raised
when in VS or VU mode instead of an illegal instruction exception.

NOTE: Many AIA features like programmable IPRIO may not be needed in resource constrained systems.
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I do not think this is the right place for this note.
It should be right where the dependency to AIA is introduced.

Since these are already controlled by WARL registers, implementations can save area by choosing to not support them. +
+
A minimal implementation of the `mvip` CSR is suggested by the AIA specification: +
"When supervisor mode is implemented, the minimal required implementation of mvien and mvip has all bits being
read-only zeros except for mvip bits 1 and 9, and sometimes bit 5, each of which is an alias of an existing
writable bit in mip. When supervisor mode is not implemented, registers mvien and mvip do not exist."

== Conditional Stack Pointer Swap extension (Smcsps, Sscsps)

The Sscsps depends on the Smcsps extension and adds the ability for conditional stack pointer swap at supervisor level and below.
Expand Down