feat(IDL): single precision floating point multiply, divide, multiply add and subtract instruction

spec/std/isa/inst/F/fdiv.s.yaml

@@ -30,7 +30,10 @@ access:
   vu: always
 data_independent_timing: true
 operation(): |
-
+  check_f_ok($encoding);
+  RoundingMode mode = rm_to_mode(rm, $encoding);
+  f[fd] = f32_div(f[fs1], f[fs2], mode);
+  mark_f_state_dirty();
 # SPDX-SnippetBegin
 # SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model <https://github.com/riscv/sail-riscv/blob/master/LICENCE>
 # SPDX-License-Identifier: BSD-2-Clause

spec/std/isa/inst/F/fmadd.s.yaml

@@ -31,6 +31,11 @@ access:
   vu: always
 data_independent_timing: true
 operation(): |
+  check_f_ok($encoding);
+  RoundingMode mode = rm_to_mode(rm, $encoding);
+  F32MulAddOp op = F32MulAddOp::Softfloat_mulAdd_addC;
+  f[fd] = f32_muladd(f[fs1], f[fs2], f[fs3], op, mode);
+  mark_f_state_dirty();
 
 # SPDX-SnippetBegin
 # SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model <https://github.com/riscv/sail-riscv/blob/master/LICENCE>

spec/std/isa/inst/F/fmsub.s.yaml

@@ -31,6 +31,11 @@ access:
   vu: always
 data_independent_timing: true
 operation(): |
+  check_f_ok($encoding);
+  RoundingMode mode = rm_to_mode(rm, $encoding);
+  F32MulAddOp op = F32MulAddOp::Softfloat_mulAdd_subC;
+  f[fd] = f32_muladd(f[fs1], f[fs2], f[fs3], op, mode);
+  mark_f_state_dirty();
 
 # SPDX-SnippetBegin
 # SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model <https://github.com/riscv/sail-riscv/blob/master/LICENCE>

spec/std/isa/inst/F/fmul.s.yaml

@@ -30,6 +30,10 @@ access:
   vu: always
 data_independent_timing: true
 operation(): |
+  check_f_ok($encoding);
+  RoundingMode mode = rm_to_mode(rm, $encoding);
+  f[fd] = f32_mul(f[fs1], f[fs2], mode);
+  mark_f_state_dirty();
 
 # SPDX-SnippetBegin
 # SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model <https://github.com/riscv/sail-riscv/blob/master/LICENCE>

spec/std/isa/inst/F/fnmadd.s.yaml

@@ -32,6 +32,11 @@ access:
   vu: always
 data_independent_timing: true
 operation(): |
+  check_f_ok($encoding);
+  RoundingMode mode = rm_to_mode(rm, $encoding);
+  F32MulAddOp op = F32MulAddOp::Softfloat_mulAdd_subC;
+  f[fd] = f32_muladd(-f[fs1], f[fs2], -f[fs3], op, mode);
+  mark_f_state_dirty();
 
 # SPDX-SnippetBegin
 # SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model <https://github.com/riscv/sail-riscv/blob/master/LICENCE>

spec/std/isa/inst/F/fnmsub.s.yaml

@@ -32,6 +32,11 @@ access:
   vu: always
 data_independent_timing: true
 operation(): |
+  check_f_ok($encoding);
+  RoundingMode mode = rm_to_mode(rm, $encoding);
+  F32MulAddOp op = F32MulAddOp::Softfloat_mulAdd_addC;
+  f[fd] = f32_muladd(-f[fs1], f[fs2], f[fs3], op, mode);
+  mark_f_state_dirty();
 
 # SPDX-SnippetBegin
 # SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model <https://github.com/riscv/sail-riscv/blob/master/LICENCE>