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This PR introduces a test generator that creates GNU Assembler test files from the RISC-V unified database. The generator produces test files in the format expected by the binutils gas test suite.

Currently the generated test files although very close to upstream test files can be incorrect due to issues like:

  1. Extension Dependencies: Instructions like ld and sd require the zilsd extension for RV32 but are incorrectly included in the base i extension tests.

  2. Assembly Field Validation: Some instructions have malformed assembly patterns in the database, leading to invalid test cases (e.g., sspopchk.x1).

For usage instructions and more information about the generator check gas_test_generator_readme.md


This is a draft PR intended to gather community feedback/suggestions on approach and priorities before investing in accuracy improvements.

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@AFOliveira AFOliveira left a comment

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Hello, @AnimeshAgarwal28.

Thanks for the PR, can you change it so that instead of merging into main, you merge it into my branch that has binutils generator? It's AFOliveira/addBinutils.

Also, if possible, can you post the artifacts this approach generates? Even if just an exapmle for the I extension.

@AnimeshAgarwal28 AnimeshAgarwal28 changed the base branch from main to AFOliveira/addBinutils September 30, 2025 10:30
@AnimeshAgarwal28 AnimeshAgarwal28 changed the base branch from AFOliveira/addBinutils to main September 30, 2025 10:37
@AnimeshAgarwal28 AnimeshAgarwal28 changed the base branch from main to AFOliveira/addBinutils September 30, 2025 11:16
@AnimeshAgarwal28 AnimeshAgarwal28 changed the base branch from AFOliveira/addBinutils to main September 30, 2025 11:19
Implement a test generator that creates GNU Assembler test files from
the RISC-V unified database. The generator produces test files in the
format expected by the binutils gas test suite.

Signed-off-by: Animesh Agarwal <[email protected]>
@AnimeshAgarwal28 AnimeshAgarwal28 changed the base branch from main to AFOliveira/addBinutils September 30, 2025 11:28
@AnimeshAgarwal28
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Hi @AFOliveira, I changed this PR to merge over your branch. I am attaching 2 sets of generated files, one for I extension and one for zicbom.:

zicbom.s:

target:
	# cbo.clean instruction
cbo.clean	(a1)
cbo.clean	(a2)
cbo.clean	(a3)

	# cbo.flush instruction
cbo.flush	(a1)
cbo.flush	(a2)
cbo.flush	(a3)

	# cbo.inval instruction
cbo.inval	(a1)
cbo.inval	(a2)
cbo.inval	(a3)

zicbom.d:

#as: -march=rv32i_zicbom
#source: zicbom.s
#objdump: -d

.*:[ 	]+file format .*


Disassembly of section .text:

0+000 <target>:
[ 	]+[0-9a-f]+:[ 	]+[0-9a-f]+[ 	]+cbo\.clean[ 	]+\(a1\)
[ 	]+[0-9a-f]+:[ 	]+[0-9a-f]+[ 	]+cbo\.clean[ 	]+\(a2\)
[ 	]+[0-9a-f]+:[ 	]+[0-9a-f]+[ 	]+cbo\.clean[ 	]+\(a3\)
[ 	]+[0-9a-f]+:[ 	]+[0-9a-f]+[ 	]+cbo\.flush[ 	]+\(a1\)
[ 	]+[0-9a-f]+:[ 	]+[0-9a-f]+[ 	]+cbo\.flush[ 	]+\(a2\)
[ 	]+[0-9a-f]+:[ 	]+[0-9a-f]+[ 	]+cbo\.flush[ 	]+\(a3\)
[ 	]+[0-9a-f]+:[ 	]+[0-9a-f]+[ 	]+cbo\.inval[ 	]+\(a1\)
[ 	]+[0-9a-f]+:[ 	]+[0-9a-f]+[ 	]+cbo\.inval[ 	]+\(a2\)
[ 	]+[0-9a-f]+:[ 	]+[0-9a-f]+[ 	]+cbo\.inval[ 	]+\(a3\)

i.s:

target:
	# add instruction
add	a0, a1, a2
add	a1, a2, a3
add	a2, a3, s0

	# addi instruction
addi	a0, a1, 1
addi	a1, a2, 2
addi	a2, a3, 3

	# and instruction
and	a0, a1, a2
and	a1, a2, a3
and	a2, a3, s0

	# andi instruction
andi	a0, a1, 1
andi	a1, a2, 2
andi	a2, a3, 3

	# auipc instruction
auipc	a0, 0
auipc	a1, 0
auipc	a2, 0

	# beq instruction
beq	a1, a2, 2
beq	a2, a3, 2
beq	a3, s0, 4

	# bge instruction
bge	a1, a2, 2
bge	a2, a3, 2
bge	a3, s0, 4

	# bgeu instruction
bgeu	a1, a2, 2
bgeu	a2, a3, 2
bgeu	a3, s0, 4

	# blt instruction
blt	a1, a2, 2
blt	a2, a3, 2
blt	a3, s0, 4

	# bltu instruction
bltu	a1, a2, 2
bltu	a2, a3, 2
bltu	a3, s0, 4

	# bne instruction
bne	a1, a2, 2
bne	a2, a3, 2
bne	a3, s0, 4

	# ebreak instruction

	# ecall instruction

	# fence.tso instruction

	# fence instruction
fence	rw, r
fence	r, w
fence	w, iorw

	# jal instruction
jal	a0, 2
jal	a1, 2
jal	a2, 4

	# jalr instruction
jalr	a0, 1(a1)
jalr	a1, 2(a2)
jalr	a2, 3(a3)

	# lb instruction
lb	a0, 1(a1)
lb	a1, 2(a2)
lb	a2, 3(a3)

	# lbu instruction
lbu	a0, 1(a1)
lbu	a1, 2(a2)
lbu	a2, 3(a3)

	# ld instruction
ld	a0, -2048(a1)
ld	a1, -2048(a2)
ld	a2, -2048(a3)

	# lh instruction
lh	a0, 1(a1)
lh	a1, 2(a2)
lh	a2, 3(a3)

	# lhu instruction
lhu	a0, 1(a1)
lhu	a1, 2(a2)
lhu	a2, 3(a3)

	# lui instruction
lui	a0, 0
lui	a1, 0
lui	a2, 0

	# lw instruction
lw	a0, 1(a1)
lw	a1, 2(a2)
lw	a2, 3(a3)

	# or instruction
or	a0, a1, a2
or	a1, a2, a3
or	a2, a3, s0

	# ori instruction
ori	a0, a1, 1
ori	a1, a2, 2
ori	a2, a3, 3

	# sb instruction
sb	a2, 1(a1)
sb	a3, 2(a2)
sb	s0, 3(a3)

	# sd instruction
sd	a2, -2048(a1)
sd	a3, -2048(a2)
sd	s0, -2048(a3)

	# sh instruction
sh	a2, 1(a1)
sh	a3, 2(a2)
sh	s0, 3(a3)

	# sll instruction
sll	a0, a1, a2
sll	a1, a2, a3
sll	a2, a3, s0

	# slli instruction
slli	a0, a1, 1
slli	a1, a2, 2
slli	a2, a3, 3

	# slt instruction
slt	a0, a1, a2
slt	a1, a2, a3
slt	a2, a3, s0

	# slti instruction
slti	a0, a1, 1
slti	a1, a2, 2
slti	a2, a3, 3

	# sltiu instruction
sltiu	a0, a1, 1
sltiu	a1, a2, 2
sltiu	a2, a3, 3

	# sltu instruction
sltu	a0, a1, a2
sltu	a1, a2, a3
sltu	a2, a3, s0

	# sra instruction
sra	a0, a1, a2
sra	a1, a2, a3
sra	a2, a3, s0

	# srai instruction
srai	a0, a1, 1
srai	a1, a2, 2
srai	a2, a3, 3

	# srl instruction
srl	a0, a1, a2
srl	a1, a2, a3
srl	a2, a3, s0

	# srli instruction
srli	a0, a1, 1
srli	a1, a2, 2
srli	a2, a3, 3

	# sub instruction
sub	a0, a1, a2
sub	a1, a2, a3
sub	a2, a3, s0

	# sw instruction
sw	a2, 1(a1)
sw	a3, 2(a2)
sw	s0, 3(a3)

	# xor instruction
xor	a0, a1, a2
xor	a1, a2, a3
xor	a2, a3, s0

	# xori instruction
xori	a0, a1, 1
xori	a1, a2, 2
xori	a2, a3, 3

i.d:

#as: -march=rv32ii
#source: i.s
#objdump: -d

.*:[ 	]+file format .*


Disassembly of section .text:

0+000 <target>:
[ 	]+[0-9a-f]+:[ 	]+[0-9a-f]+[ 	]+add[ 	]+a0,\ a1,\ a2
[ 	]+[0-9a-f]+:[ 	]+[0-9a-f]+[ 	]+add[ 	]+a1,\ a2,\ a3
[ 	]+[0-9a-f]+:[ 	]+[0-9a-f]+[ 	]+add[ 	]+a2,\ a3,\ s0
[ 	]+[0-9a-f]+:[ 	]+[0-9a-f]+[ 	]+addi[ 	]+a1,\ a1,\ 1
[ 	]+[0-9a-f]+:[ 	]+[0-9a-f]+[ 	]+addi[ 	]+a1,\ a2,\ 2
[ 	]+[0-9a-f]+:[ 	]+[0-9a-f]+[ 	]+addi[ 	]+a2,\ a3,\ 3
[ 	]+[0-9a-f]+:[ 	]+[0-9a-f]+[ 	]+and[ 	]+a0,\ a1,\ a2
[ 	]+[0-9a-f]+:[ 	]+[0-9a-f]+[ 	]+and[ 	]+a1,\ a2,\ a3
[ 	]+[0-9a-f]+:[ 	]+[0-9a-f]+[ 	]+and[ 	]+a2,\ a3,\ s0
[ 	]+[0-9a-f]+:[ 	]+[0-9a-f]+[ 	]+andi[ 	]+a0,\ a1,\ 1
[ 	]+[0-9a-f]+:[ 	]+[0-9a-f]+[ 	]+andi[ 	]+a1,\ a2,\ 2
[ 	]+[0-9a-f]+:[ 	]+[0-9a-f]+[ 	]+andi[ 	]+a2,\ a3,\ 3
[ 	]+[0-9a-f]+:[ 	]+[0-9a-f]+[ 	]+auipc[ 	]+a0,\ 0
[ 	]+[0-9a-f]+:[ 	]+[0-9a-f]+[ 	]+auipc[ 	]+a1,\ 0
[ 	]+[0-9a-f]+:[ 	]+[0-9a-f]+[ 	]+auipc[ 	]+a2,\ 0
[ 	]+[0-9a-f]+:[ 	]+[0-9a-f]+[ 	]+beq[ 	]+a1,\ a2,\ 2
[ 	]+[0-9a-f]+:[ 	]+[0-9a-f]+[ 	]+beq[ 	]+a2,\ a3,\ 2
[ 	]+[0-9a-f]+:[ 	]+[0-9a-f]+[ 	]+beq[ 	]+a3,\ s0,\ 4
[ 	]+[0-9a-f]+:[ 	]+[0-9a-f]+[ 	]+bge[ 	]+a1,\ a2,\ 2
[ 	]+[0-9a-f]+:[ 	]+[0-9a-f]+[ 	]+bge[ 	]+a2,\ a3,\ 2
[ 	]+[0-9a-f]+:[ 	]+[0-9a-f]+[ 	]+bge[ 	]+a3,\ s0,\ 4
[ 	]+[0-9a-f]+:[ 	]+[0-9a-f]+[ 	]+bgeu[ 	]+a1,\ a2,\ 2
[ 	]+[0-9a-f]+:[ 	]+[0-9a-f]+[ 	]+bgeu[ 	]+a2,\ a3,\ 2
[ 	]+[0-9a-f]+:[ 	]+[0-9a-f]+[ 	]+bgeu[ 	]+a3,\ s0,\ 4
[ 	]+[0-9a-f]+:[ 	]+[0-9a-f]+[ 	]+blt[ 	]+a1,\ a2,\ 2
[ 	]+[0-9a-f]+:[ 	]+[0-9a-f]+[ 	]+blt[ 	]+a2,\ a3,\ 2
[ 	]+[0-9a-f]+:[ 	]+[0-9a-f]+[ 	]+blt[ 	]+a3,\ s0,\ 4
[ 	]+[0-9a-f]+:[ 	]+[0-9a-f]+[ 	]+bltu[ 	]+a1,\ a2,\ 2
[ 	]+[0-9a-f]+:[ 	]+[0-9a-f]+[ 	]+bltu[ 	]+a2,\ a3,\ 2
[ 	]+[0-9a-f]+:[ 	]+[0-9a-f]+[ 	]+bltu[ 	]+a3,\ s0,\ 4
[ 	]+[0-9a-f]+:[ 	]+[0-9a-f]+[ 	]+bne[ 	]+a1,\ a2,\ 2
[ 	]+[0-9a-f]+:[ 	]+[0-9a-f]+[ 	]+bne[ 	]+a2,\ a3,\ 2
[ 	]+[0-9a-f]+:[ 	]+[0-9a-f]+[ 	]+bne[ 	]+a3,\ s0,\ 4
[ 	]+[0-9a-f]+:[ 	]+[0-9a-f]+[ 	]+fence[ 	]+rw,\ r
[ 	]+[0-9a-f]+:[ 	]+[0-9a-f]+[ 	]+fence[ 	]+r,\ w
[ 	]+[0-9a-f]+:[ 	]+[0-9a-f]+[ 	]+fence[ 	]+w,\ iorw
[ 	]+[0-9a-f]+:[ 	]+[0-9a-f]+[ 	]+jal[ 	]+a0,\ 2
[ 	]+[0-9a-f]+:[ 	]+[0-9a-f]+[ 	]+jal[ 	]+a1,\ 2
[ 	]+[0-9a-f]+:[ 	]+[0-9a-f]+[ 	]+jal[ 	]+a2,\ 4
[ 	]+[0-9a-f]+:[ 	]+[0-9a-f]+[ 	]+jalr[ 	]+a0,\ 1\(a1\)
[ 	]+[0-9a-f]+:[ 	]+[0-9a-f]+[ 	]+jalr[ 	]+a1,\ 2\(a2\)
[ 	]+[0-9a-f]+:[ 	]+[0-9a-f]+[ 	]+jalr[ 	]+a2,\ 3\(a3\)
[ 	]+[0-9a-f]+:[ 	]+[0-9a-f]+[ 	]+lb[ 	]+a0,\ 1\(a1\)
[ 	]+[0-9a-f]+:[ 	]+[0-9a-f]+[ 	]+lb[ 	]+a1,\ 2\(a2\)
[ 	]+[0-9a-f]+:[ 	]+[0-9a-f]+[ 	]+lb[ 	]+a2,\ 3\(a3\)
[ 	]+[0-9a-f]+:[ 	]+[0-9a-f]+[ 	]+lbu[ 	]+a0,\ 1\(a1\)
[ 	]+[0-9a-f]+:[ 	]+[0-9a-f]+[ 	]+lbu[ 	]+a1,\ 2\(a2\)
[ 	]+[0-9a-f]+:[ 	]+[0-9a-f]+[ 	]+lbu[ 	]+a2,\ 3\(a3\)
[ 	]+[0-9a-f]+:[ 	]+[0-9a-f]+[ 	]+ld[ 	]+a0,\ \-2048\(a1\)
[ 	]+[0-9a-f]+:[ 	]+[0-9a-f]+[ 	]+ld[ 	]+a1,\ \-2048\(a2\)
[ 	]+[0-9a-f]+:[ 	]+[0-9a-f]+[ 	]+ld[ 	]+a2,\ \-2048\(a3\)
[ 	]+[0-9a-f]+:[ 	]+[0-9a-f]+[ 	]+lh[ 	]+a0,\ 1\(a1\)
[ 	]+[0-9a-f]+:[ 	]+[0-9a-f]+[ 	]+lh[ 	]+a1,\ 2\(a2\)
[ 	]+[0-9a-f]+:[ 	]+[0-9a-f]+[ 	]+lh[ 	]+a2,\ 3\(a3\)
[ 	]+[0-9a-f]+:[ 	]+[0-9a-f]+[ 	]+lhu[ 	]+a0,\ 1\(a1\)
[ 	]+[0-9a-f]+:[ 	]+[0-9a-f]+[ 	]+lhu[ 	]+a1,\ 2\(a2\)
[ 	]+[0-9a-f]+:[ 	]+[0-9a-f]+[ 	]+lhu[ 	]+a2,\ 3\(a3\)
[ 	]+[0-9a-f]+:[ 	]+[0-9a-f]+[ 	]+lui[ 	]+a0,\ 0
[ 	]+[0-9a-f]+:[ 	]+[0-9a-f]+[ 	]+lui[ 	]+a1,\ 0
[ 	]+[0-9a-f]+:[ 	]+[0-9a-f]+[ 	]+lui[ 	]+a2,\ 0
[ 	]+[0-9a-f]+:[ 	]+[0-9a-f]+[ 	]+lw[ 	]+a0,\ 1\(a1\)
[ 	]+[0-9a-f]+:[ 	]+[0-9a-f]+[ 	]+lw[ 	]+a1,\ 2\(a2\)
[ 	]+[0-9a-f]+:[ 	]+[0-9a-f]+[ 	]+lw[ 	]+a2,\ 3\(a3\)
[ 	]+[0-9a-f]+:[ 	]+[0-9a-f]+[ 	]+or[ 	]+a0,\ a1,\ a2
[ 	]+[0-9a-f]+:[ 	]+[0-9a-f]+[ 	]+or[ 	]+a1,\ a2,\ a3
[ 	]+[0-9a-f]+:[ 	]+[0-9a-f]+[ 	]+or[ 	]+a2,\ a3,\ s0
[ 	]+[0-9a-f]+:[ 	]+[0-9a-f]+[ 	]+ori[ 	]+a0,\ a1,\ 1
[ 	]+[0-9a-f]+:[ 	]+[0-9a-f]+[ 	]+ori[ 	]+a1,\ a2,\ 2
[ 	]+[0-9a-f]+:[ 	]+[0-9a-f]+[ 	]+ori[ 	]+a2,\ a3,\ 3
[ 	]+[0-9a-f]+:[ 	]+[0-9a-f]+[ 	]+sb[ 	]+a2,\ 1\(a1\)
[ 	]+[0-9a-f]+:[ 	]+[0-9a-f]+[ 	]+sb[ 	]+a3,\ 2\(a2\)
[ 	]+[0-9a-f]+:[ 	]+[0-9a-f]+[ 	]+sb[ 	]+s0,\ 3\(a3\)
[ 	]+[0-9a-f]+:[ 	]+[0-9a-f]+[ 	]+sd[ 	]+a2,\ \-2048\(a1\)
[ 	]+[0-9a-f]+:[ 	]+[0-9a-f]+[ 	]+sd[ 	]+a3,\ \-2048\(a2\)
[ 	]+[0-9a-f]+:[ 	]+[0-9a-f]+[ 	]+sd[ 	]+s0,\ \-2048\(a3\)
[ 	]+[0-9a-f]+:[ 	]+[0-9a-f]+[ 	]+sh[ 	]+a2,\ 1\(a1\)
[ 	]+[0-9a-f]+:[ 	]+[0-9a-f]+[ 	]+sh[ 	]+a3,\ 2\(a2\)
[ 	]+[0-9a-f]+:[ 	]+[0-9a-f]+[ 	]+sh[ 	]+s0,\ 3\(a3\)
[ 	]+[0-9a-f]+:[ 	]+[0-9a-f]+[ 	]+sll[ 	]+a0,\ a1,\ a2
[ 	]+[0-9a-f]+:[ 	]+[0-9a-f]+[ 	]+sll[ 	]+a1,\ a2,\ a3
[ 	]+[0-9a-f]+:[ 	]+[0-9a-f]+[ 	]+sll[ 	]+a2,\ a3,\ s0
[ 	]+[0-9a-f]+:[ 	]+[0-9a-f]+[ 	]+slli[ 	]+a0,\ a1,\ 1
[ 	]+[0-9a-f]+:[ 	]+[0-9a-f]+[ 	]+slli[ 	]+a1,\ a2,\ 2
[ 	]+[0-9a-f]+:[ 	]+[0-9a-f]+[ 	]+slli[ 	]+a2,\ a3,\ 3
[ 	]+[0-9a-f]+:[ 	]+[0-9a-f]+[ 	]+slt[ 	]+a0,\ a1,\ a2
[ 	]+[0-9a-f]+:[ 	]+[0-9a-f]+[ 	]+slt[ 	]+a1,\ a2,\ a3
[ 	]+[0-9a-f]+:[ 	]+[0-9a-f]+[ 	]+slt[ 	]+a2,\ a3,\ s0
[ 	]+[0-9a-f]+:[ 	]+[0-9a-f]+[ 	]+slti[ 	]+a0,\ a1,\ 1
[ 	]+[0-9a-f]+:[ 	]+[0-9a-f]+[ 	]+slti[ 	]+a1,\ a2,\ 2
[ 	]+[0-9a-f]+:[ 	]+[0-9a-f]+[ 	]+slti[ 	]+a2,\ a3,\ 3
[ 	]+[0-9a-f]+:[ 	]+[0-9a-f]+[ 	]+sltiu[ 	]+a0,\ a1,\ 1
[ 	]+[0-9a-f]+:[ 	]+[0-9a-f]+[ 	]+sltiu[ 	]+a1,\ a2,\ 2
[ 	]+[0-9a-f]+:[ 	]+[0-9a-f]+[ 	]+sltiu[ 	]+a2,\ a3,\ 3
[ 	]+[0-9a-f]+:[ 	]+[0-9a-f]+[ 	]+sltu[ 	]+a0,\ a1,\ a2
[ 	]+[0-9a-f]+:[ 	]+[0-9a-f]+[ 	]+sltu[ 	]+a1,\ a2,\ a3
[ 	]+[0-9a-f]+:[ 	]+[0-9a-f]+[ 	]+sltu[ 	]+a2,\ a3,\ s0
[ 	]+[0-9a-f]+:[ 	]+[0-9a-f]+[ 	]+sra[ 	]+a0,\ a1,\ a2
[ 	]+[0-9a-f]+:[ 	]+[0-9a-f]+[ 	]+sra[ 	]+a1,\ a2,\ a3
[ 	]+[0-9a-f]+:[ 	]+[0-9a-f]+[ 	]+sra[ 	]+a2,\ a3,\ s0
[ 	]+[0-9a-f]+:[ 	]+[0-9a-f]+[ 	]+srai[ 	]+a0,\ a1,\ 1
[ 	]+[0-9a-f]+:[ 	]+[0-9a-f]+[ 	]+srai[ 	]+a1,\ a2,\ 2
[ 	]+[0-9a-f]+:[ 	]+[0-9a-f]+[ 	]+srai[ 	]+a2,\ a3,\ 3
[ 	]+[0-9a-f]+:[ 	]+[0-9a-f]+[ 	]+srl[ 	]+a0,\ a1,\ a2
[ 	]+[0-9a-f]+:[ 	]+[0-9a-f]+[ 	]+srl[ 	]+a1,\ a2,\ a3
[ 	]+[0-9a-f]+:[ 	]+[0-9a-f]+[ 	]+srl[ 	]+a2,\ a3,\ s0
[ 	]+[0-9a-f]+:[ 	]+[0-9a-f]+[ 	]+srli[ 	]+a0,\ a1,\ 1
[ 	]+[0-9a-f]+:[ 	]+[0-9a-f]+[ 	]+srli[ 	]+a1,\ a2,\ 2
[ 	]+[0-9a-f]+:[ 	]+[0-9a-f]+[ 	]+srli[ 	]+a2,\ a3,\ 3
[ 	]+[0-9a-f]+:[ 	]+[0-9a-f]+[ 	]+sub[ 	]+a0,\ a1,\ a2
[ 	]+[0-9a-f]+:[ 	]+[0-9a-f]+[ 	]+sub[ 	]+a1,\ a2,\ a3
[ 	]+[0-9a-f]+:[ 	]+[0-9a-f]+[ 	]+sub[ 	]+a2,\ a3,\ s0
[ 	]+[0-9a-f]+:[ 	]+[0-9a-f]+[ 	]+sw[ 	]+a2,\ 1\(a1\)
[ 	]+[0-9a-f]+:[ 	]+[0-9a-f]+[ 	]+sw[ 	]+a3,\ 2\(a2\)
[ 	]+[0-9a-f]+:[ 	]+[0-9a-f]+[ 	]+sw[ 	]+s0,\ 3\(a3\)
[ 	]+[0-9a-f]+:[ 	]+[0-9a-f]+[ 	]+xor[ 	]+a0,\ a1,\ a2
[ 	]+[0-9a-f]+:[ 	]+[0-9a-f]+[ 	]+xor[ 	]+a1,\ a2,\ a3
[ 	]+[0-9a-f]+:[ 	]+[0-9a-f]+[ 	]+xor[ 	]+a2,\ a3,\ s0
[ 	]+[0-9a-f]+:[ 	]+[0-9a-f]+[ 	]+xori[ 	]+a0,\ a1,\ 1
[ 	]+[0-9a-f]+:[ 	]+[0-9a-f]+[ 	]+xori[ 	]+a1,\ a2,\ 2
[ 	]+[0-9a-f]+:[ 	]+[0-9a-f]+[ 	]+xori[ 	]+a2,\ a3,\ 3

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AFOliveira commented Sep 30, 2025

Are you only generating valid tests? I.e. not generating test that are supposed to fail? Per example, wrong number of operans, wrong operand type.

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AnimeshAgarwal28 commented Sep 30, 2025

No, the generator attempts to generate failing tests also (Currently the generator only generates invalid_operands errors), here is an example:

i-fail.l:

.*: Assembler messages:
.*: Error: illegal operands `add x32, x33, a2'
.*: Error: illegal operands `addi x32, x33, 1'
.*: Error: illegal operands `addi a0, a1, 999999'
.*: Error: illegal operands `addiw x32, x33, 1'
.*: Error: illegal operands `addiw a0, a1, 999999'
.*: Error: illegal operands `addw x32, x33, a2'
.*: Error: illegal operands `and x32, x33, a2'

i-fail.s

target:
	add	x32, x33, a2
	addi	x32, x33, 1
	addi	a0, a1, 999999
	addiw	x32, x33, 1
	addiw	a0, a1, 999999
	addw	x32, x33, a2
	and	x32, x33, a2

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codecov bot commented Sep 30, 2025

Codecov Report

✅ All modified and coverable lines are covered by tests.
✅ Project coverage is 46.05%. Comparing base (87e0992) to head (1823a4f).

Additional details and impacted files
@@                   Coverage Diff                   @@
##           AFOliveira/addBinutils    #1139   +/-   ##
=======================================================
  Coverage                   46.05%   46.05%           
=======================================================
  Files                          11       11           
  Lines                        4942     4942           
  Branches                     1345     1345           
=======================================================
  Hits                         2276     2276           
  Misses                       2666     2666           
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In general, I think there's some dead code like the one I pointed out, can you verify this is isn't the case or fix it if you find more?

@ThinkOpenly ThinkOpenly added the generators Related to backend/generator label Oct 2, 2025
@ThinkOpenly ThinkOpenly moved this to In progress in UDB Generators Oct 3, 2025
Signed-off-by: Animesh Agarwal <[email protected]>
@AnimeshAgarwal28 AnimeshAgarwal28 changed the title feat(backends): Add GNU Assembler Test Generator for RISC-V feat(backends): add GNU Assembler Test Generator for RISC-V Oct 9, 2025
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Trying something - @claude is all dead code removed?

@AFOliveira AFOliveira requested a review from Copilot October 11, 2025 16:59
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Pull Request Overview

This PR introduces a GNU Assembler test generator that automatically creates test files for the RISC-V toolchain from the unified database. The generator aims to streamline testing of RISC-V extensions by producing assembly source files, dump files, and error test cases in the format expected by the binutils gas test suite.

Key changes:

  • Adds comprehensive test generator with constraint-aware assembly generation and realistic operand combinations
  • Creates documentation detailing usage, architecture, and integration instructions
  • Implements modular design with separate components for instruction grouping, assembly generation, and test orchestration

Reviewed Changes

Copilot reviewed 2 out of 2 changed files in this pull request and generated 5 comments.

File Description
gas_test_generator_readme.md Documentation covering usage, features, architecture, and extension guidelines
gas_test_generator.py Main implementation with instruction loading, constraint extraction, assembly generation, and test file creation

Tip: Customize your code reviews with copilot-instructions.md. Create the file or learn how to get started.

- normalize extension tokens, extract dependencies from definedBy, and
  carry them into each instruction group
- replace ad-hoc fail lists with structured error cases, reason tags
- emit annotated pass and no-alias dumps from a single primary example
  selection per instruction

Signed-off-by: Animesh Agarwal <[email protected]>
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@AnimeshAgarwal28 can you solve copilot's review?

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@AnimeshAgarwal28 Is this the version that you already tested on binutils and that compiled?

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Yes, a lot of the generated tests work as expected, there are still issues with some of the extensions. For eg. c-d.s does not pass because of a hyphen in the march string, this needs to be addressed.

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Ok, please let me know when you need help or a review!

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