Skip to content
Open
Show file tree
Hide file tree
Changes from all commits
Commits
File filter

Filter by extension

Filter by extension

Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
1 change: 1 addition & 0 deletions riscv/csrs.cc
Original file line number Diff line number Diff line change
Expand Up @@ -1847,6 +1847,7 @@ ssp_csr_t::ssp_csr_t(processor_t* const proc, const reg_t addr, const reg_t mask
void ssp_csr_t::verify_permissions(insn_t insn, bool write) const {
masked_csr_t::verify_permissions(insn, write);
DECLARE_XENVCFG_VARS(SSE);
auto p = proc; // To match macro usage
require_envcfg(SSE);
}

Expand Down
2 changes: 1 addition & 1 deletion riscv/decode_macros.h
Original file line number Diff line number Diff line change
Expand Up @@ -193,7 +193,7 @@ static inline bool is_aligned(const unsigned val, const unsigned pos)
#define require_envcfg(field) \
do { \
if (((STATE.prv != PRV_M) && (m##field == 0)) || \
((STATE.prv == PRV_U && !STATE.v) && (s##field == 0))) \
(p->extension_enabled('S') && (STATE.prv == PRV_U && !STATE.v) && (s##field == 0))) \
throw trap_illegal_instruction(insn.bits()); \
else if (STATE.v && ((h##field == 0) || \
((STATE.prv == PRV_U) && (s##field == 0)))) \
Expand Down